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sinara-hw / Kasli-SOC

Xilinx ZynQ(R) version of Kasli FPGA controller.
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Undefined behavior with SPI devices on several EEM ports #74

Closed thomasfire closed 1 year ago

thomasfire commented 1 year ago

We've been struggling with the issue that EEM ports 2-7 and 10-11 often fail to work with Samplers, Zotinos, Mirnies and probably some others. It appears that these ports are LVDS_18 and not LVDS_25, which are used in RISCV Kasli and other ports on Kasli-SoC. Which leads to the devices fail to recognize the signal because it may be lower than a threshold. Also it seems to be a limitation on Zynq chips https://docs.xilinx.com/v/u/en-US/ug475_7Series_Pkg_Pinout .

Are there any solutions or workarounds about this?

gkasprow commented 1 year ago

You cannot use LVDS_18 with 2.5V supply on Kasli. Artix devices support LVDS only on 2.5V ports. 1.8V LVDS ports are supported only in KIntex HP banks. Kasli SoC banks 12,13 use 2.5V and LVDS25 because these are HR banks banks 33,34,35 use 1.8V and LVDS18 because these are HP banks

thomasfire commented 1 year ago

Are there any workarounds/fixes possible? It is quite annoying problem for us

gkasprow commented 1 year ago

Just use right primitives dedicated to bank types. It is not a bug

gkasprow commented 1 year ago

I might have an idea of what is going on. Don't these modules use the same LVDS drivers? When working with Sayma, I noticed the strange behaviour of 3.3V LVDS transceivers when working with 1.8V banks. The FPGA bank voltage was elevated to over 2V instead of 1.8V, which was caused by abnormal LVDS transceiver behaviour. The LVDS transceiver sometimes produced a 3V level on the differential pair when inactive. When active, the level was around 1.2V which is the desired level for LVDS.

thomasfire commented 1 year ago

Appeared to be gateware issue https://git.m-labs.hk/M-Labs/artiq-zynq/issues/197 , resolved with https://github.com/m-labs/artiq/commit/29cb7e785d94cbb6f0633f9195560b92c0eed335