DIOT(CPCI) version of Kasli SOC

[gkasprow]

The Kasli SOC with DIOT adapter resembles Frankenstein creation and has several limitations (not enough LVDS pairs). For this reason we will develop native KASLI SOC DIOT board. The idea is to use bigger 7 Series SoC with enough pins to support 8 x 16 DIOT peripherals. Rest remains the same. This will keep compatibility with existing Kasli. Or, shall we implement some extra features?

[jordens]

Let's do this. Could you propose a rough block diagram or schematic sketch that we can iterate on? Is there no OHWR/CERN DIOT system board with a SoC that we could align with?

[marmeladapk]

We'll probably take a lot from DIOT System Board ( https://ohwr.org/project/diot-sb-zu/).

śr., 11 paź 2023, 23:12 użytkownik Robert Jördens @.***> napisał:

Let's do this. Could you propose a rough block diagram or schematic sketch that we can iterate on? Is there no OHWR/CERN DIOT system board with a SoC that we could align with?

— Reply to this email directly, view it on GitHub https://github.com/sinara-hw/Kasli-SOC/issues/76#issuecomment-1758549317, or unsubscribe https://github.com/notifications/unsubscribe-auth/AF3AQXELNIJUNBGJNCL66TTX64DSLANCNFSM6AAAAAA54JRRYY . You are receiving this because you are subscribed to this thread.Message ID: @.***>

[gkasprow]

We will only replace EEM connectors with CPCIS ones and use bigger FPGA. Rest remains the same. An important feature is correct power sequencing that should improve Kasli's survivability.

[jordens]

Having reviewed the DIOT sys board it looks like we can take it as is.

[jordens]

... especially if the planned changes for v3 land (RJ45 to PS, USB for JTAG/I2C etc).