search

sinara-hw / Kasli

Kasli is a powerful FPGA carrier, capable of controlling 12 Eurocard extension modules.
Other
16 stars 1 forks source link

Kasli/v1.1 clock distribution #16

Closed gkasprow closed 5 years ago

gkasprow commented 5 years ago

From @jordens on March 7, 2018 19:33

The single ended clock outputs on board have gotten quite a bit noisier than in v1.0. Haven't checked AM vs PM. And the 440 kHz spur from before is now at 300 kHz. This is opticlock with free_run.

png1

Copied from original issue: sinara-hw/sinara#525

gkasprow commented 5 years ago

From @jordens on March 7, 2018 19:34

I don't think I changed the Si5324 parameters w.r.t. the previous Kasli/v1.0 tests.

gkasprow commented 5 years ago

From @hartytp on March 7, 2018 20:14

Ouch. What do the power rails look like?

gkasprow commented 5 years ago

From @hartytp on March 7, 2018 20:15

Can you check am v pm by clocking urukul off it?

gkasprow commented 5 years ago

From @jordens on March 7, 2018 20:46

From Kasli/v1.1 125 MHz

Urukul-AD9912/v1.1

png4

Urukul-AD9910/v1.1

png3

From Kasli/v1.0 125 MHz

Urukul-AD9912/v1.1

png1

But I probably won't have time to dig into this in the next couple of days anyway.

gkasprow commented 5 years ago

Is the onboard oscillator turned off? There is dedicated CPLD pin for that purpose.

gkasprow commented 5 years ago

Ups, I mixed it with Urukul :)

gkasprow commented 5 years ago

From @marmeladapk on March 7, 2018 21:13

The single ended clock outputs on board have gotten quite a bit noisier

All outputs look similar?

What do the power rails look like?

I'm esp. interested in P2V5 LDO and P12V0 before and after filter. Unfortunately we're out of Kaslis at the moment so I can't measure that myself.

gkasprow commented 5 years ago

From @jordens on March 7, 2018 21:56

I tested at least three of the four. And the 12v supply was a pretty clean linear one.

gkasprow commented 5 years ago

From @hartytp on March 8, 2018 10:41

@marmeladapk Looking over the Kasli schematic again, it seems that all the filter inductors after the SMPS are actually ferrite beads. They are about 100R at 100MHz, but probably <1Ohm at a few hundred kHz (from a quick skim of the data sheet, I didn't see a Z versus frequency curve, so that's just a guess), so probably they're not actually doing much at all for the noise frequencies Robert is looking at. Also, the filter capacitors aren't that large (6V 22uF is probably <10uF with a 3.3V bias).

Having said that, we have a good drop out for that LDO, so I would expect its PSRR to be excellent at a few hundred kHz.

The only think I can think of is that the PSRR of either the Si5324 of the clock buffer is much worse at Vcc=2V5 than at Vcc=3V3. As a temorary fix, we could try changing the 2V5 regulator set point to 3V3 and wiring it to run directly from the 12V supply. That's quick to do, and would confirm this as a PSRR issue (I'm happy to do that once my V1.1 Kasli arrives).

gkasprow commented 5 years ago

From @hartytp on March 8, 2018 10:41

either way, good catch @jordens