During the rise of power supplies the V_IO supply voltage must remain less than or equal to the V_CC supply voltage.
Changing power sequence to bring 3V3 after 1V0 would also allow to ramp 1V8 after 1V0 and 2V5 after 1V8, which would be in line with Xilinx suggested sequence (current sequence is acceptable, but may cause higher current draw during power-on).
S25FL128S (FPGA memory) datasheet states:
Changing power sequence to bring 3V3 after 1V0 would also allow to ramp 1V8 after 1V0 and 2V5 after 1V8, which would be in line with Xilinx suggested sequence (current sequence is acceptable, but may cause higher current draw during power-on).