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sinara-hw / Kasli

Kasli is a powerful FPGA carrier, capable of controlling 12 Eurocard extension modules.
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DC couple the Si5324 into the ADCLK #52

Closed hartytp closed 4 years ago

hartytp commented 4 years ago

Why AC-couple it? Having a well-defined DC level at the clock buffer input would help to avoid oscillations (the Si5324 can be shutdown from software giving a logic low at the input, so won't oscillate unlike the buffers)

marmeladapk commented 4 years ago

@hartytp Currently Si5324 outputs are configured as LVDS on all boards in ARTIQ and LVDS has different common level than LVPECL.

Also this:

The LVPECL outputs are “LVPECL compatible.” No DC biasing circuitry is required to drive a standard LVPECL load.

and this:

It is recommended that the outputs be ac coupled to avoid common mode issues.

from Si53xx reference manual doesn't give me much confidence in DC coupling those outputs. I'd leave it as it is unless you have seen problems caused by current coupling.