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sinara-hw / Kasli

Kasli is a powerful FPGA carrier, capable of controlling 12 Eurocard extension modules.
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schematic review #53

Closed hartytp closed 4 years ago

hartytp commented 4 years ago

@marmeladapk I looked at the schematics. They look good!

I've raised a few issues, mainly with questions. Other that that LGTM. NB however I haven't done the kind of thorough review I've done for the EEMs (checking every pin on every IC, reference designs, etc), I assume that wasn't expected for this release.

@sbourdeauducq @WeiDaZhang can you sign off on the WR parts?

@jordens @sbourdeauducq are you happy to sign off on the design over all?

gkasprow commented 4 years ago
sbourdeauducq commented 4 years ago 
* is there any reason to keep the SATA connector?

We use it for connecting two Kasli in the same crate with DRTIO. It's a somewhat uncommon use case though.

gkasprow commented 4 years ago

Now you can do the same with sfp patchcord

hartytp commented 4 years ago

We use it for connecting two Kasli in the same crate with DRTIO. It's a somewhat uncommon use case though.

Doing that inside the rack (rather than using external patch coards) feels a bit niche to warrant keeping the SFP IMHO.

hartytp commented 4 years ago

@jordens @sbourdeauducq have you signed off on this design review?

jordens commented 4 years ago

Looks good to me. I checked general I2C design, SFP digital design. Minor things:

jordens commented 4 years ago

Oh. And excellent work on the git commit messages, changelog, and issue tracking @marmeladapk ! Thanks.

hartytp commented 4 years ago

Does it make sense to go for the Si53340-B-GM instead of ADCLK948 IC1 and add two more MMCX clock outs? We use it on Urukul already. And it can run at 2.5 V which may make ditching the Si5324 together with its supply more efficient later.

Fine by me. @WeiDaZhang any objections.

@WeiDaZhang please can you confirm that you're happy to sign off on the clocking part of this design asap (apologies if you've already done that!).

Other than that, I'm happy to sign off

hartytp commented 4 years ago

@WeiDaZhang did you check the rest of the clocking? (I think you did this ages ago, but want to double check you still happy) If so, we just need @sbourdeauducq to sign off on the WR PLL implementation from his side and then I think all reviews are complete.

Would be great to get this off to manufacture in the next week or so

WeiDaZhang commented 4 years ago

Fine by me. @WeiDaZhang any objections.

We measured before that ADCLK948 has flicker phase noise of -145dBc/Hz@10kHz offset at 1GHz carrier. Si53340-B-GM seems to be -137dBc/Hz@10kHz offset at 312MHz, which is slightly worse.

Our WR is no better than 1x10^-13 mod Allan, which about -120dBc/Hz@10kHz offset at 312MHz. So, should not make any difference.

jordens commented 4 years ago

The 125 MHz clock goes through a Si53340-B-GM+Si53312-B-GM combo on Urukul in any case. I am uncertain where else you could see the increase. This is more a question of cost/thermal/power supply simplicity, leaving it to @marmeladapk

hartytp commented 4 years ago

Yes. This is the kind of thing that would have worried me a year ago, but I think we now understand the performance bottlenecks well enough to know that this will not be a limitation (eg compared to the transceiver pll)

@WeiDaZhang are you happy to sign off on the complete design?

WeiDaZhang commented 4 years ago

Yes. This is the kind of thing that would have worried me a year ago, but I think we now understand the performance bottlenecks well enough to know that this will not be a limitation (eg compared to the transceiver pll)

@WeiDaZhang are you happy to sign off on the complete design?

Happy

hartytp commented 4 years ago

Cool so we just need @sbourdeauducq to sign off on the wr connections and then the review is complete

sbourdeauducq commented 4 years ago

Except for the support for CMOS Si549 oscillators, this looks OK to me.

hartytp commented 4 years ago

@marmeladapk Okay, everyone has now completed their reviews. So...when can this go to manufacture?

hartytp commented 4 years ago

@marmeladapk heads up: the grant we used to pay for our creotech kaslis expires soon so we need to get them to manufacture ASAP to avoid problems

hartytp commented 4 years ago

Ping @marmeladapk @gkasprow we really need to get kasli 2.0 sent to manufacture in the next week before the grant that paid for the work ends. This is very important to us. In any case, it seems like almost all the work is done already

marmeladapk commented 4 years ago

@hartytp Layout and schematics are finished.

hartytp commented 4 years ago

Nice!

I've had a skim over the schematics and it looks good to me. I haven't done the usual thorough design review (check every pin description, eval board/ref design, pin abs max ratings, required capacitances, etc etc) as I'm assuming you did that @marmeladapk

@WeiDaZhang can you sign off on the WR/clocking please?

@sbourdeauducq @jordens are you happy with this revision? I'd like to send boards to manufacture on monday if possible.

hartytp commented 4 years ago

@marmeladapk can you remind me which areas had changes? It's worth us carefully reviewing all changes to ensure we don't break anything...

hartytp commented 4 years ago

I went over the clock page one last time (the only page that has significant changes that I feel qualified to review). Other than cosmetics I don't see any issues.

Any objections to cutting this release on Monday morning?

WeiDaZhang commented 4 years ago

I went over the clock page one last time (the only page that has significant changes that I feel qualified to review). Other than cosmetics I don't see any issues.

Any objections to cutting this release on Monday morning?

May I ask why that? image Select the power between 2.5/3.3 I suppose. If so, shall we use P3V3_LDO1 instead then, as Si549s shall not be used at the same time when Si5324 is in use.

hartytp commented 4 years ago

Thanks @marmeladapk!

I'm assuming everyone has completed their reviews (@WeiDaZhang @sbourdeauducq @jordens ) so we can close this and go to manufacture on Monday once the last straggling issues are closed.

hartytp commented 4 years ago

I saw a box labelled Kasli 2 at CTI so I guess this exists now...

hartytp commented 4 years ago

@marmeladapk we really need these in our lab ASAP. When can you ship them?

marmeladapk commented 4 years ago

@hartytp I don't even have them on my desk. Do you really want us to send you untested hardware without panels? AFAIK we should receive Kaslis on Monday from production (it's currently during inspection).

Besides you should write to Anna about this not to me, as it's her decision not mine when to ship it.

hartytp commented 4 years ago

Thanks for the update. Please do test before shipping. Okay, so if receive them on Monday, is it realistic to think that testing will be complete by end of next week?

akaminska commented 4 years ago

Hi Tom @hartytp , Kasli is still in optical inspection after production. We should get the boards for testing Tuesday morning. We will keep you posted on the progress.

hartytp commented 4 years ago

Great! Thanks for the update.

marmeladapk commented 4 years ago

@hartytp @jordens

IMG_20200304_110615__01

IMG_20200304_113328__01

This SFP cage is massive.

We're now validating if our tests work correctly with the new hardware.

sbourdeauducq commented 4 years ago

Looks good! Where is the fan plugged?

marmeladapk commented 4 years ago

J21, above the FPGA. (2-pin header). Currently the pins are too short, but I plan to change them to header with key, which won't allow reverse connection.

hartytp commented 4 years ago

Awesome, looks beautiful! Good job @marmeladapk

hartytp commented 4 years ago

When do the panels arrive?

akaminska commented 4 years ago

On Monday at the latest.

jordens commented 4 years ago

Re availability of the SFP cages: I noticed that even Cisco would use two 2x1 cages next to each other when they need 4 SFP and not a 2x2. And what are we going to do with all the unused space when we go to cPCIs...

gkasprow commented 4 years ago

CPCIS is not an issue because Kasli would be rotated 180degs and the panel can still be 8HP

jordens commented 4 years ago

I'm not worried about panel space (and for 4 HP, the cooling stack may or may not be in the way as well). I was wondering whether there is anything useful we can do with all the unused space of the IDC rats nest which occupies half the entire board area.

marmeladapk commented 4 years ago

Most of that space will still be required to escape from under the bga package. But perhaps we could make Kasli and other CPCIS boards shorter (160mm)?

gkasprow commented 4 years ago

The idea behind existing Kasli was to add simple adapter that converts EEMs to CPCI.

jordens commented 4 years ago

I think it will be much better to draw a line and transition a sufficient set of several modules to cPCIs in one go without adapters.

gkasprow commented 4 years ago

Yes, but for the moment essential part of the community seems to be happy with existing solution

jordens commented 4 years ago

The community that M-Labs and QUARTIQ serve would very much appreciate a better solution.

marmeladapk commented 4 years ago

The community that M-Labs and QUARTIQ serve would very much appreciate a better solution.

Great! I really like the mechanics of CPCIS crate.

Kasli v1.1 gateware with uart pins moved to new positions:

Initializing SDRAM...
Read leveling scan:
Module 1:
00000000000111111111110000000000
Module 0:
00000000000111111111110000000000
Read leveling: 16+-5 16+-5 done
SDRAM initialized
Memory test passed

Booting from flash...
Starting firmware.
[     0.000004s]  INFO(satman): ARTIQ satellite manager starting...
[     0.005612s]  INFO(satman): software ident 5.0.dev+848.g2a909839.dirty;satellite
[     0.013025s]  INFO(satman): gateware ident 5.0.dev+848.g2a909839.dirty;satellite
panic at src/libcore/result.rs:945:5: cannot initialize Si5324: "Si5324 failed to ack write address"

SDRAM works. I also moved I2C SDA. It seems that I2C works at least initially (no I2C switch error). We'll test this further using our test bench.

akaminska commented 4 years ago

From the point of view of managing hardware production and stocks, focusing on a specific format of cards for the future instead of having two versions of most cards would make life easier

hartytp commented 4 years ago

Awesome @marmeladapk

Re cpics: I can see this being what we want long term but would be nice to have a play with the adapter boards and existing eems before making a decision

gkasprow commented 4 years ago

this is exactly what we do right now. 3 adapters would be needed to serve all EEM boards.