[x] IC23A missing from schematic, set as a GND follower to keep from floating
[x] IC27B missing from schematic, used later in this issue
[x] IC26C missing from schematic, short both inputs to GND
[x] IC26D missing from schematic, short both inputs to GND
[x] IC8A missing from schematic, short both inputs to GND
[x] IC8C missing from schematic, used later in this issue
[x] IC8D missing from schematic, used later in this issue
Opamps with unmached input inpedances
[x] IC40B inverting input connected directly to output, needs ~12k2 (10k + 2k2 can be used)
[x] IC14A inverting input connected directly to output, needs 1k
Diagnostic circuits
ADC dividers (R183/R184, R187/R185, R188/R186) are set to 10k/8k06 and cap out at 11.2V, while ~12V can be measured.
Choosing from values already in the project, 31k6/20k divider will allow up to 12.9V.
[x] R183, R187, R188 changed to 31k6 0.1%
[x] R184, R185, R186 changed to 20k 0.1%
[x] to leave filter unchanged, C46/C47/C48 should be changed from 1u to ~360n, 2x 100n should be fine
IC25C compares DAC setting and I_meas in opposing phases, causing V_limit_P and V_limit_N to always be on.
[x] signals at R98/R107 should be crossed
Schematic for reference (v1.0 board)
CH1 - R103 (I_meas), CH2 - R109 (DAC_OUT), +-1A 100Hz sine into a shorted output
After crossing:
DAC output:
When using internal DAC, the 0/5V DAC output is inverted, and scaled to -5/5V. With the output current proportional to -DAC_Vout, this works out to the output current being directly proportional to DAC code.
When using external DAC, the input signal is not inverted.
[x] R86 should be mounted
[x] R86/R87 should be changed to 0.1% resistors (2k reused from R88/R89)
Schematic for reference (v1.0 board)
Buck_Vout switch issues:
T1/T17 drivers create a 10k:10k divider (R134/R203 and R202/R204) placed at the transistor gate. With the lowest IC13 output voltage (4V) the T17 transistor does not fully open. Given the 20V G-S rating of SI4425DDY-T1-GE3
[x] both R203 and R204 can be changed to ~100R
Power stage
Last stage transistors (T19/T20 and T6/T9) are supplied from GND/Buck_Vout, and are driven by IC19 + T3/T5 and T8/T12 supplied from P15V0/N6V0. With load impedance too high for the set Buck_Vout voltage (especially when output is disconnected) IC19 tends to go to the very rails, which causes either T3/T12 or T5/T8 to turn on very hard, and causes T19/T9 or T20/T6 to work as a base-collector diode - burning a lot of power and locking itself in this state at one of the rails. This either raises the Buck_Vout and/or raises the N6V0 rail, pulling PG low.
Inserting series diodes at outer stage collectors (with added capacitance after the diodes, at the collectors) fixes this issue, but burns a lot of power at high currents and shortens the output voltage range.
At the same time, when driving high output currents (during tests: more than +-3A range), T3/T8 seem to take a lot of current (based on thermal camera), causing IC49 to eventually pull PG low and disable the P15V0 rail. This affects the opamps in diagnostics section, and falsely raises PWR_lim diode.
IC19 and T3/T5/T8/T12 can be potentially swapped from P15V0/N6V0 to GND/Buck_Vout, to prohibit this from happening and to not add any additional heat generators to the board (some output voltage range will be lost as well). This would require:
increasing Buck_Vout values from 4V/8V/10V/12V above 4.5V (minimal OPA2197IDGKR supply)
limiting IC14B output to stay within 0-Buck_Vout
IC14Bs output is always equal to +-5V (Vin=set current) + Buck_Vout/2 (Ref). Assuming that lowest Buck_Vout value is changed from 4V to 5V, this means that in worst case it ranges from -2.5V to 7.5V at 0/5V IC19 supply. If Vin were to be initially divided from +-5V to +-2V, this would give at least a 0.5V headroom from each rail - this can be later corrected by increasing the gain (RN1A/RN1D = 20k, RN1B/RN1C = 1k):
$Iout = -1k/20k/R19 * Vin$
With Vin scaled by $2/5$, R19 (0.05R) should be decreased by $5/2$ to 0.02R (with the same RN1 ratio), or decreased by $4/5$ to 0.04R (RN1 ratio changed to 10:1)
Schematic for reference (v1.0 board):
PG signal
There are several issues with the PG signal. For reference: it is asserted by IC49 (N6V0/P15V0), IC21 (P5V4A), IC13 (Buck_Vout), is pulled up by R123 to P3V3_MP, and it sets the LD5 LED, resets the IC36 IO expander, clears DAC output and disables the 5V reference voltage.
[x] no pullups/pulldowns at IC36 IO expander outputs (Ref_Sel_0, Ref_Sel_1, VSEL_0, VSEL_1), IOs set as inputs by default - this leaves IC13 output (Buck_Vout) in an undefined state (feedback controlled by VSEL_0/VSEL_1) and pulls PG low. It would be best to default at the lowest IC13 output voltage (all IC36 outputs high).
[x] when using internal DAC, a PG drop will cause the DAC output to reset back to 0x0000 - which corresponds to -5A at the output driver. It would probably be better to stay at whatever setting pulled PG low. A better safety mechanism would be to disable the Buck_Vout rail - included in one of further fixes.
[x] a low PG will disable the internal 5V reference (IC11/IC20), used to derive various other voltages: the DAC output, derived 2/4/5/6V reference for the power stage, and derived references in the diagnostics ADC circuitry. This will cause ADC diagnostics to be lost along with power/voltage limit signals. Same as with the DAC, it would probably be better to leave it enabled.
[x] VSEL_0/1 signals set Buck_Vout voltage to 4/8/10/12 V. When set to 12V (VSEL_0 = 0, VSEL_1 = 0), IC13 is disabled (RUN low), and T1/T17 are set to bypass it (T1 on, T17 off). Tying RUN pin low also pulls PG output low (internally in IC13). When hard-wired high, PG is also pulled low as the buck converter is not able to generate a 12V output (set via R76) due to minimal dropout. When set for a lower output voltage, P12V0 back-feeds via the parasitic diode in T17 and raises VOUT voltage - also pulling PG low. For other Buck_Vout voltages, during transition IC13 output is momentarily not matched with the connected feedback resistors - causing PG to drop and reset IC36 IO expander, reverting the change.
Schematic for reference (v1.0 board):
CH1 - PG signal, CH2 - Buck_Vout power rail, IC36 reset forced high
With partial solution (IC13 disconnected from PG at 12V output)
Those issues can be fixed by disconnecting PG net from IC13 when configured for a 12V output, and by adding an ignore window (after changing VSEL_0/1) with a duration longer than ~150ms (too long for a realistic RC filter). IC8/IC26/IC27 (quad OR, dual monostable multivibrator) have unused resources in the mounted packages, and were used for the solution.
BOM Count reduction
Many passives are only used once, many components have close values, and several values are unnecessarily used in different packages.
The board is not densly populated, it will be easy to correct the below.
Reductions in resistor values:
[x] R210 100k (10k/100k divider) changed to 10k (R200/R215 10k changed to 1k)
[x] R207 47k (3k3/47k divider) replaced with (3k/) 33k+10k
[x] R135 31k6 (10k/31k6 divider) replaced with (24k/)75k
[ ] R11, R142 2x27k replaced with 24k+20k+10k
[x] R76, R168, R190 replaced 20k with 2x 10k
[x] R42 13k replaced with 10k + 3k
[x] R136 10k (10k/31k6 divider) replaced with 24k(/75k)
CannaCardo
commented
1 month ago
Unused/ floating resources
Opamps with unmached input inpedances
Diagnostic circuits
ADC dividers (R183/R184, R187/R185, R188/R186) are set to 10k/8k06 and cap out at 11.2V, while ~12V can be measured. Choosing from values already in the project, 31k6/20k divider will allow up to 12.9V.
IC25C compares DAC setting and I_meas in opposing phases, causing V_limit_P and V_limit_N to always be on.
Schematic for reference (v1.0 board)
CH1 - R103 (I_meas), CH2 - R109 (DAC_OUT), +-1A 100Hz sine into a shorted output
After crossing:
DAC output:
When using internal DAC, the 0/5V DAC output is inverted, and scaled to -5/5V. With the output current proportional to -DAC_Vout, this works out to the output current being directly proportional to DAC code. When using external DAC, the input signal is not inverted.
Schematic for reference (v1.0 board)
Buck_Vout switch issues:
T1/T17 drivers create a 10k:10k divider (R134/R203 and R202/R204) placed at the transistor gate. With the lowest IC13 output voltage (4V) the T17 transistor does not fully open. Given the 20V G-S rating of SI4425DDY-T1-GE3
Power stage
Last stage transistors (T19/T20 and T6/T9) are supplied from GND/Buck_Vout, and are driven by IC19 + T3/T5 and T8/T12 supplied from P15V0/N6V0. With load impedance too high for the set Buck_Vout voltage (especially when output is disconnected) IC19 tends to go to the very rails, which causes either T3/T12 or T5/T8 to turn on very hard, and causes T19/T9 or T20/T6 to work as a base-collector diode - burning a lot of power and locking itself in this state at one of the rails. This either raises the Buck_Vout and/or raises the N6V0 rail, pulling PG low.
Inserting series diodes at outer stage collectors (with added capacitance after the diodes, at the collectors) fixes this issue, but burns a lot of power at high currents and shortens the output voltage range.
At the same time, when driving high output currents (during tests: more than +-3A range), T3/T8 seem to take a lot of current (based on thermal camera), causing IC49 to eventually pull PG low and disable the P15V0 rail. This affects the opamps in diagnostics section, and falsely raises PWR_lim diode.
IC19 and T3/T5/T8/T12 can be potentially swapped from P15V0/N6V0 to GND/Buck_Vout, to prohibit this from happening and to not add any additional heat generators to the board (some output voltage range will be lost as well). This would require:
IC14Bs output is always equal to +-5V (Vin=set current) + Buck_Vout/2 (Ref). Assuming that lowest Buck_Vout value is changed from 4V to 5V, this means that in worst case it ranges from -2.5V to 7.5V at 0/5V IC19 supply. If Vin were to be initially divided from +-5V to +-2V, this would give at least a 0.5V headroom from each rail - this can be later corrected by increasing the gain (RN1A/RN1D = 20k, RN1B/RN1C = 1k):
$Iout = -1k/20k/R19 * Vin$
With Vin scaled by $2/5$, R19 (0.05R) should be decreased by $5/2$ to 0.02R (with the same RN1 ratio), or decreased by $4/5$ to 0.04R (RN1 ratio changed to 10:1)
Schematic for reference (v1.0 board):
PG signal
There are several issues with the PG signal. For reference: it is asserted by IC49 (N6V0/P15V0), IC21 (P5V4A), IC13 (Buck_Vout), is pulled up by R123 to P3V3_MP, and it sets the LD5 LED, resets the IC36 IO expander, clears DAC output and disables the 5V reference voltage.
[x] no pullups/pulldowns at IC36 IO expander outputs (Ref_Sel_0, Ref_Sel_1, VSEL_0, VSEL_1), IOs set as inputs by default - this leaves IC13 output (Buck_Vout) in an undefined state (feedback controlled by VSEL_0/VSEL_1) and pulls PG low. It would be best to default at the lowest IC13 output voltage (all IC36 outputs high).
[x] when using internal DAC, a PG drop will cause the DAC output to reset back to 0x0000 - which corresponds to -5A at the output driver. It would probably be better to stay at whatever setting pulled PG low. A better safety mechanism would be to disable the Buck_Vout rail - included in one of further fixes.
[x] a low PG will disable the internal 5V reference (IC11/IC20), used to derive various other voltages: the DAC output, derived 2/4/5/6V reference for the power stage, and derived references in the diagnostics ADC circuitry. This will cause ADC diagnostics to be lost along with power/voltage limit signals. Same as with the DAC, it would probably be better to leave it enabled.
[x] VSEL_0/1 signals set Buck_Vout voltage to 4/8/10/12 V. When set to 12V (VSEL_0 = 0, VSEL_1 = 0), IC13 is disabled (RUN low), and T1/T17 are set to bypass it (T1 on, T17 off). Tying RUN pin low also pulls PG output low (internally in IC13). When hard-wired high, PG is also pulled low as the buck converter is not able to generate a 12V output (set via R76) due to minimal dropout. When set for a lower output voltage, P12V0 back-feeds via the parasitic diode in T17 and raises VOUT voltage - also pulling PG low. For other Buck_Vout voltages, during transition IC13 output is momentarily not matched with the connected feedback resistors - causing PG to drop and reset IC36 IO expander, reverting the change.
Schematic for reference (v1.0 board):
CH1 - PG signal, CH2 - Buck_Vout power rail, IC36 reset forced high
With partial solution (IC13 disconnected from PG at 12V output)
Those issues can be fixed by disconnecting PG net from IC13 when configured for a 12V output, and by adding an ignore window (after changing VSEL_0/1) with a duration longer than ~150ms (too long for a realistic RC filter). IC8/IC26/IC27 (quad OR, dual monostable multivibrator) have unused resources in the mounted packages, and were used for the solution.
BOM Count reduction
Many passives are only used once, many components have close values, and several values are unnecessarily used in different packages. The board is not densly populated, it will be easy to correct the below.
Reductions in resistor values:
Summary of all R values in the board (crossed lines can be removed):
100k06031%1R2101247k04021%1R2074513R13527k04021%2R11, R1421371320k06031%3R76, R168, R19013k04021%1R421924R136, (...)345010k06030.1%4R105, R183, R187, R18810k04021%2140, 1418k0606030.1%3R184, R185, R1867k506031%1R935k604021%1R1395k106031%1R1895k104021%2R170, R1944k9906031%1R41124k704021%1R1633k306031%1R1004967362k204021%2R1, R42k06030.1%3R48, R88, R891k604021%2R58, R1431k506031%1R92126171k04021%4R17, R22, R87, R18222006031%9R6, R9, R20, R28, R29, R33, R118, R119, R12122020004021%1R510006031%4R79, R81, R83, R851718571004021%1R16413006032R129, R130Total of 25 positions removed
Reductions in capacitor values:
Summary of all C values in the board (crossed lines can be removed):
6722uF060320% / 6.3V1C79X5R10uF080510% / 16V2X5R2510uF060310% / 10V1C167X5R1uF120610% / 50V1C14X7R8181uF060310% / 16V7X7R1uF040210% / 16V2C71, C81X5R4154100nF040210% / 16V13X7R47pF04021% / 50V1C67NP047Total of 8 positions removed
Other BOM count reductions: