PCB DRC - Githubissues

sinara-hw / Metlino

microTCA carrier hub (MCH) Tongue 3 FPGA module with HVDCI and SFP

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PCB DRC #43

Closed marmeladapk closed 5 years ago

marmeladapk commented 5 years ago

Solder mask sliver constraint (IC4) drc_1_soldermask

Rules:

Disable silk to silk clearance constraint?
Shouldn't minimum annular ring be 0,1mm?
Add rule about matching length within all differential pair to say 2mm?
Shouldn MCH_FABRIC_D signals be also length matched (don't know if they are matched in backplane)?

gkasprow commented 5 years ago

we don't care about GTH links length matching. Altium calculates annular ring in a strange way. 0.1/0.3mm vias generate errors when the rule is set to more than 50um.