sinara-hw / Phaser

Quad channel 1GS/s RF generator card with dual IQ upconverter and dual 5MS/s ADC and FPGA in EEM form factor
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Phase noise measurement #125

Closed sotirova closed 3 years ago

sotirova commented 3 years ago

Setup

Measurement results

First look at phase noise when phaser is using its internal clock vs when it is given an external 125 MHz clock as described above. For both of these measurements Kasli was connected to an external 125 MHz reference as above. image

For reference, here is also the phase noise from the Kasli MMCX clock outputs when using the Kasli internal clock vs when Kasli takes an external 125 MHz reference. image

hartytp commented 3 years ago

Kasli 125 MHz ext ref from CLK SYN of R&S SMA 100A

Interesting. Do you know/did you ever measure what the phase noise spectrum of that output is? I recall it being significantly worse than the main output, but can't find any info in the spec sheet.

hartytp commented 3 years ago

Anyway, that's lovely data and generally better than I'd expected. From a physics perspective, that's plenty good enough for everything I want to do, which is great.

In terms of background curiosity/calibrating expectations for what should be doable for this kind of design, the AD9910 noise graphs with and w/o PLL are copied below. My understanding is that DDS chips like the AD9910 are generally about as good as one gets for this kind of digital synthesis so are a pretty good reference.

image

Looks like phaser is within 10dB of the AD9910 at all frequencies, a bit better than the 9910 at higher frequencies and a bit worse at lower frequencies, but broadly comparable throught.

image

Phase with PLL is something like 20dB worse than the AD9910 w/o PLL for close-in noise with less than 10dB between them for broader-band noise.

As a general point of interest, I'd be curious to know what the noise spectrum of phaser looks like without the PLL, but that requires a bit of reconfiguration is is not something we need to worry about.

hartytp commented 3 years ago

Anyway, good work @sotirova! I don't see anything suspicious here (the DAC data sheet doesn't have phase noise plots so doesn't give us anything to directly compare with, but I don't see anything in the above to suggest we're doing worse than I'd expect).

sotirova commented 3 years ago

Thanks for the comments @hartytp!

Interesting. Do you know/did you ever measure what the phase noise spectrum of that output is? I recall it being significantly worse than the main output, but can't find any info in the spec sheet.

Here's the phase noise of the synth RF OUT and CLK SYN for reference - indeed the CLK SYN looks worse than the main RF output synth

hartytp commented 3 years ago

Here's the phase noise of the synth RF OUT and CLK SYN for reference - indeed the CLK SYN looks worse than the main RF output

What carrier frequency?

sotirova commented 3 years ago

What carrier frequency?

125 MHz both, as used in the setup

hartytp commented 3 years ago

anyway, good to know that the CLK SYN phase noise is not a limitation here (although not by that far)

pathfinder49 commented 3 years ago

I've performed similar measurements for the Phaser-Upconverter variant.

My setup:

\ Using external reference distributed by Kasli Using dedicated phaser reference
Phaser Reference Clock Kasli 125MHz ext ref
Phaser 2875 MHz Local Oscillator Lo 2875 MHz LO 2875 MHz ext clock
Phaser 3.2123 GHz output RF 3212-3 MHz with LO 2875 MHz RF 3212-3 MHz with LO 2875 MHz ext clock

At ~3 GHz, the broadband output phase-noise within 1 MHz is dominated by the TRF-LO phase noise. The phase noise can be improved substantially by using a dedicated frequency reference.