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sinara-hw / Phaser

Quad channel 1GS/s RF generator card with dual IQ upconverter and dual 5MS/s ADC and FPGA in EEM form factor
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DSP Block Diagram #128

Closed RHanley1 closed 1 year ago

RHanley1 commented 3 years ago

It would be useful if there was a functional block diagram of the DSP to give a nice overview of phaser. There is an old diagram in #1 , however I believe this is not quite up-to-date with the latest release. Does an up-to-date diagram exist?

hartytp commented 3 years ago

@RHanley1 I agree that a block diagram of the DSP would be good. However, this probably isn't the right place for that discussion. We tend to use the hw repos for discussions about hardware, but your question relates to a specific gateware implementation. Better to ask this question at either quartiq/phaser or m-labs/artiq

RHanley1 commented 3 years ago

This has been posted in Quartiq/phaser (https://github.com/quartiq/phaser/issues/16). Would probably be worthwhile putting a link to the quartiq wiki?

jordens commented 1 year ago

Closing as invalid here and addressed elsewhere.