v1.1 and v1.1.1 changelog - Githubissues

sinara-hw / Phaser

Quad channel 1GS/s RF generator card with dual IQ upconverter and dual 5MS/s ADC and FPGA in EEM form factor

13 stars 4 forks source link

v1.1 and v1.1.1 changelog #134

Open gkasprow opened 3 years ago

gkasprow commented 3 years ago

v1.1 changelog

R181 swapped with R180 #100
R255 swapped with R256 #100
R220=10k #100
fixed schematic annotation #103
fixed sikscreen #104
fixed FP label #105
changed SMT MMCX connectors to u.fl ones #106
added fan PWM circuit #107 #126
all LEDs moved to the board edge
moved CPCIS adapter clock connector to keep compatibility with Urukul
fixed power budget #109
fixed baseband load resistors #110
fixed issue with SMT distance and solderability in several places #117
fixed some crosstalk issues #118
moved DAC termination resistors closer to IC #120
+/-12 converter replaced with 1W version with lower losses #121
J9 aligned #124

v1.1.1 changelog

fixed VCC_LOx #131
added LEDs annotation on PCB and FP #132