DAC and up-converter mismatched, no support for DC

[jbqubit]

Our choice of DAC (DAC34H84) and PLL-Mixer (TRF372017) preclude passing DC to the TRF. AFAICT TI has specific recommendations for DAC-PLL/mixer pairings but we didn't follow it. I don't recall the design choices that led to this pairing but it appears there is no resolution possible with the current chip pair.

current filter network

Phaser v1.1 coupling between DAC and TRS looks like this.

This matches (approximately) the recommendation of the specification sheet for the TRF. In this approach the TRF chips provides it's own bias (1.7 V) to the I and Q inputs. In this mode the TRF also has DACs for trimming needed to achieve carrier feedthrough cancellation. However, this approach precludes IQ modulation that depends on DC from the DAC.

DAC can't supply 1.7V

TI provides an example filter network in the case that the DC-TRF coupling is DC-pass.

However, we can't use this approach because the maximum output of our DAC is -0.5 V and 0.6 V (for the differential outputs, spec sheet 6.5 Output compliance range).

pull-up resistor option

A TI application note discusses building a filter network with pull-up resistors (p 7). This would attenuate the DC component of the DAC by at least 0.5.

one motivation: PDH ESB locking

One application of Phaser is to generate phase modulation suitable for PDH electronic sideband locking (ESB) [0].

A way to do this with Phaser is phase modulated I and Q. However, this has a DC component that is blocked by the current filter network.

Ref

[0] Thorpe, J. I., Numata, K. & Livas, J. Laser frequency stabilization and control through offset sideband locking to optical cavities. Opt. Express 16, 15980 (2008).

[gkasprow]

There is one way of shifting the DC signal without attenuating it - use of current sources. 10R resistors are needed to equalize the Vbe differences between transistors. Such circuit of 3 thermally coupled transistors is nearly insensitive to temperature The output current is equal to the input current. 1k gives roughly 4.3mA of current at every output. To get 1.7V one must add roughly 1V to the DAC output. 220R resistor will create such drop on the capacitor. The 1U capacitor will make passing AC without losses. I'd add a trimpot which can be used to tune the DC to be exactly 1.7V. The only problem is 91R termination resistor. But since the distance between DAC and TRF is 4cm, we can get rid of it.

[gkasprow]

I'd add inductors to decouple from BJT capacitances

[jbqubit]

How flat is the response of this approach for frequencies below cutoff of the 1 uF cap?

[gkasprow]

Should be flat up to dc. May need LC tuning. I can simulate it if you consider this solution.

[jbqubit]

May need LC tuning.

In an IQ context the phase response is important.

@restelli may have comments on the current bias approach you've suggested.

[hartytp]

@gkasprow let's not do this for phaser. It's a now a well tested design in production that covers a wide range of use-cases. This is a pretty invasive change for a nice use case that's likely to result in performance regressions. If people major changes like this we should start a new project.

[gkasprow]

Sure, the circuit I described can be added to the existing design easily for this particular use case.

[hartytp]

@jbqubit apologies if that came out a bit negative. It's been my repeated experience with these Sinara boards that one needs to constantly fight scope creep. These boards aren't going to cover every use and that's okay. If you want a more major design change, feel free to fork the project or look at one of the other sinara designs like Sayma which has a wider remit.

[jbqubit]

What is the -3dB corner for the current coupling between DAC and TRS? I'll add this to the wiki documentation for v1.0 and v1.1.