T6-T9 NMOS transistors (driven from P12V0 - always existing) does not separate P3V3_MP and P3V3 domains when the power supply circuits onboard are off.
It causes that the I2C lines on P3V3_MP side are loaded (voltage drop) by P3V3 domain eg. when thermal shutdown occured and LM75 shutted down the supply. Then it is sometimes impossible to write to LM75 sensors and clear the over temperature condition.
Solution: drive the NMOS from another voltage, generated onboard.
gkasprow
commented
1 year ago
T6-T9 NMOS transistors (driven from P12V0 - always existing) does not separate P3V3_MP and P3V3 domains when the power supply circuits onboard are off. It causes that the I2C lines on P3V3_MP side are loaded (voltage drop) by P3V3 domain eg. when thermal shutdown occured and LM75 shutted down the supply. Then it is sometimes impossible to write to LM75 sensors and clear the over temperature condition.
Solution: drive the NMOS from another voltage, generated onboard.