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sinara-hw / Phaser

Quad channel 1GS/s RF generator card with dual IQ upconverter and dual 5MS/s ADC and FPGA in EEM form factor
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Input clock baluns #63

Closed jordens closed 4 years ago

jordens commented 4 years ago

The input clock balun design should follow https://github.com/sinara-hw/Kasli/issues/50: Support floating the SMA/MMCX shields by connecting the shield to the balun tap and common to ground with a dnp jumper (and not the balun tap and the shield independently to GND). Keeping it the baluns DNP and bypassed and the SMA/MMCX shields grounded by default is fine with me.

gkasprow commented 4 years ago

done. I also changed the transformers to TC2-1TX+

hartytp commented 4 years ago

NB this also needs to be implemented correctly in the layout so keeping open for now

gkasprow commented 4 years ago

done in layout as well obraz