Closed gkasprow closed 5 years ago
P3V3 rail
P1V8 rail
P1V5 after heavy optimization
P1V2
P12V0 after heavy optimization. I managed to reduce losses twice.
we cannot do much with power density because it is dominated by the power pins in the AMC connector
ALl simulations were performed using Hyperlynx VX2.3 VCCINT after optimization. The VCCINT is measured and stabilized under the FPGA, but I made sure the drop is the lowest possible. Ivccint = 10A