HT3 manufacturing, baseline testing

[jbqubit]

HT3 is hardware testing phase that is conducted by the hardware vendor. Details are discussed in the Sayma v2 hardware contract. TS2 and TS7 refer to crate configurations detailed here.

Create independent Issues to track tests and report observations as appropriate.

The contracts funds the printing, stuffing PCB quantities as follow.

• Metlino AMC v1.0: print 10 PCBs, stuff 4
  • [ ] printing complete
  • [ ] stuffing complete
• Sayma AMC v2.0: print 10 PCBs, stuff 6
  • [ ] printing complete
  • [ ] stuffing complete
• Sayma RTM v2.0: print 10 PCBs, stuff 6
  • [ ] printing complete
  • [ ] stuffing complete
• BaseMod v2.0: print 20 PCBs, stuff 12
  • [ ] printing complete
  • [ ] stuffing complete
• TestMod v2.0: print 6 PCBs, stuff 6
  • [ ] printing complete
  • [ ] stuffing complete

Testing of all stuffed PCBs:

• Thermal test in TS7

  • [ ] maximum temperature of measured integrated circuits (IC) < 65 C. Monitor temperature of a subset of ICs using Module Management Controller (MMC)

• MMC configuration including power supply sequencing and IPMI. Contractor shall test MMC firmware on TS7 system prior to distribution.

  • [ ] Publish MCH configuration file used for these tests with TS-MTCA and NATIVE-R5.
  • [ ] Intelligent Platform Management Interface (IPMI).
  • [ ] crate power-on with all boards and with arbitrary RTM unplugged in TS7
  • [ ] Hot swap arbitrary AMC and RTM boards in TS7
  • [ ] Power-on with or without RTM unplugged in TS1

• Signal integrity testing using any suitable FPGA intellectual property (IP) (eg Xilinx) for all ICs. Tested individually. Design and implement test to simulate heavy loading of a system configured as TS2. Two TestMod PCBs are to be installed dissipating representative power for all tests. Tests will simultaneously exercise the following subsystems.

  • [ ] Inter-Integrated Circuit (I2C), serial peripheral interface (SPI), address all ICs round robin at full speed
  • [ ] AD built-in DAC JESD pseudo-random binary sequence (PRB)S test at ten (10) gigabits per second (Gb/s) lane for both DACs
  • [ ] SDRAM PRBS write-then-read
  • [ ] AMC backplane ethernet PRBS at 1 GSPS
  • [ ] Small Form-factor Pluggable (SFP) loop-back PRBS at 6 Gb/s
  • [ ] AMC backplane PRBS at 6 Gb/s
  • [ ] FPGA Mezzanine Card (FMC) loop-back
  • [ ] Realistic FPGA fabric load and clock activity

When testing is complete ship hardware to ARL or designated partner labs.

The hardware contractor retains the following PCBs for testing and as backups in case of system integrator hardware failure: 2 Sayma AMC, 2 Sayma RTM, 4 BaseMod, 1 Metlino.

If errors arise after shipping of hardware, Contractor shall debug and test on TS2.

[marmeladapk]

@jbqubit It seems that you didn't update test plan with our stress test that we sent you. Can I update your post with it?