Open sbourdeauducq opened 4 years ago
They are just in case. There is a note below that explains this. LVDS is just a routing rule. At the moment the single-ended SSTL18 is populated, so do not use the differential ones. It is a source terminated.
Currently I cannot get any signal out of those FFs. The FPGA constraints I am using are:
Subsignal("rec_clk", Pins("F12"), IOStandard("SSTL18_I")),
Subsignal("main_xo", Pins("L9"), IOStandard("SSTL18_I"))
Are they correct?
They look fine. Please, look with fast scope at the pins 14, 15 and 16, 17 of IC19. If you don't have such fast scopes, measure DC voltages instead.
@marmeladapk did you check this circuit?
@sbourdeauducq We checked DDMTD_OUT_MAIN_CLK_SSTL18
. And the signal that we got out of it looked fine. We used the same IO standard as you. Do you have both main and helper clock signals?
With CDR we had a problem to get clock out of MGT. It didn't work on the first few tries, so we moved to other issues.
I have both working now (since today). The GTH needs this: https://github.com/m-labs/artiq/commit/307a6ca140b1cea8cf0c08072fb733312de6fd0a
Another issue was this: https://github.com/m-labs/artiq/commit/14e09582b6ea141624d3f50d85498d4590f55c7c
@sbourdeauducq Can we close this?
Just two issues remain:
I created separate issue about the misleading LVDS label. https://github.com/sinara-hw/Sayma_AMC/issues/143
@sbourdeauducq Can this be closed?
No, there should still be a decision about which signal (SE or differential) to keep, and then remove the other.
Why are there both single-ended SSTL18 connections and differential SSTL15? Which one is populated on the boards?
Also this indication of "LVDS" is misleading:
@gkasprow