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sinara-hw / Sayma_RTM

RTM board with 8-channel GS/s DAC, 125MS/s ADC and flexible clock circuit
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swapping FPGA banks 14 and 34 #44

Closed gkasprow closed 5 years ago

gkasprow commented 5 years ago

@sbourdeauducq I've just discovered that "When CFGBVS is connected to GND, the VCCO of Bank 0 must be 1.8V, and if the I/O in Banks 14 or 15 are used for configuration, then the VCCO for the Banks (14 and 15) must also be 1.8V. Violating this rule will result in configuration failures." Since we use 3V3 config levels, bank 14w where CFG_DIN is must be also connected to 3V3. So I want to swap bank 14 and bank 34. They have identical properties. I will update xls pin files

sbourdeauducq commented 5 years ago

Urgh, good catch.

gkasprow commented 5 years ago

I changed also power delivery to the banks so can close it.