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sinara-hw / Sayma_RTM

RTM board with 8-channel GS/s DAC, 125MS/s ADC and flexible clock circuit
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GPIO/debug port #51

Closed sbourdeauducq closed 5 years ago

sbourdeauducq commented 5 years ago

Can we have a GPIO header going to the FPGA where we can connect signals in case of unexpected problems? Include GC pins, and differential pairs.

gkasprow commented 5 years ago

We already have. I moved it to another bank to have access to SRCC and MRCC clock pins. I will also route them as diff pairs. The CLK50 was moved to the 3V3 bank. obraz