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sinara-hw / Sayma_RTM

RTM board with 8-channel GS/s DAC, 125MS/s ADC and flexible clock circuit
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PI analysis #87

Closed gkasprow closed 5 years ago

gkasprow commented 5 years ago

P2V0 rail under 150% load obraz We are well within the LDO limit. But current density in some places is too high. obraz LDOs were shorted to simulate the whole PDN. After optimization, the current density does not exceed 55A/mm2 obraz and DC drop was lowered twice. Note that most of the DC drop is caused by the inductor DCR obraz

gkasprow commented 5 years ago

P4V0 PDN after optimization via current obraz

current density obraz

DC drop is mainly on DCR obraz

gkasprow commented 5 years ago

P6V0 rail after optimization DC drop is dominated by inductors DCR obraz

The current density is slightly high, but lower than 67A/mm2. It cannot be easily lowered. obraz

gkasprow commented 5 years ago

N12V0A PDN. Nothing to optimize obraz obraz

gkasprow commented 5 years ago

P12V0A Nothing to optimize

gkasprow commented 5 years ago

N6V0: 28mV drop, max I density 22.8A/mm2, I optimized the dropout slightly,

gkasprow commented 5 years ago

P3V3 looked bad before optimization. After some tweaking it is OK: drop is dominated by inductors DCR obraz

dnadlinger commented 5 years ago

Out of curiosity, is this HyperLynx? I'm sure I've seen this UI somewhere before…

gkasprow commented 5 years ago

@dnadlinger Yes, it is. Very similar results are produced by SiWave, but it does not have the 3D mode.

gkasprow commented 5 years ago

12V rail before optimization obraz obraz

and after some tweaking obraz

gkasprow commented 5 years ago

P1V0. Reduction of the drop from 220mV to 57mV obraz

gkasprow commented 5 years ago

P1V2 obraz

gkasprow commented 5 years ago

P2V5 obraz