v1.0 rc2 design review

[hartytp]

https://github.com/sinara-hw/Stabilizer/releases/tag/v0.9rc2

[cjbe]

@gkasprow can we move the MMCX digital inputs to pads with timer capture-compare inputs. E.g. move DI1 and DI2 to PA3 and PA8.

(This will allow precise time-stamping of the digital inputs)

[cjbe]

@gkasprow can we use a X2C64A instead of the 32A - this is pin compatible, and gives us a lot more headroom for prototyping.

[hartytp]

@gkasprow I think that everyone who is interested in giving feedback on this design has now given feedback. The main outstanding thing from my POV is finalising the board-board connectors for the AFEs. Other than that, feel free to close this design review whenever you want.

[gkasprow]

I will, but now Sayma has higher priority.

[cjbe]

I have had another look for board-to-board interconnects, and it seems like the Samtec ESW-1xx-33-L-D are the best option. They don't seem to be generally stocked by most distributors, but several (Digikey, Mouser, Farnell) offers them on a 3 week lead direct-ship from Samtec, which is good enough.

I definitely think it is better to use some slightly longer lead-time connectors to keep the analog / GPIO / AGPIO connectors mechanically incompatible.

[cjbe]

@gkasprow it would be very useful if the ADC/DAC header (J1) was moved up or down, or further away from the front panel - even 3mm would help. In its current position space for components on the front panel is quite cut up:

[gkasprow]

I can shift it by 5mm easily. Would it be sufficient? 10mm is also possible with some work.

[dtcallcock]

I don't see v1.0rc2 in the releases. Am I missing something @gkasprow ?

[gkasprow]

There was no v1.0rc2 yet. So far there was only v0.9rc2.

[dtcallcock]

I see v0.9rc2 and v1.0rc1. Which one should be looking at?

[gkasprow]

v1.0rc1

[cjbe]

@gkasprow 5mm would be perfect.

[cjbe]

@gkasprow it would be useful if the P12V0A and N12V0A rails are brought out to the "ADC and DAC header" (instead of P/N13V0S).

This means that a minimal piggyback board with a couple of op-amps on would not need to have any additional regulators on.

[dtcallcock]

• Can DI0/DI1 use a 5V-tolerant buffer to offer more flexibility on what random lab boxes can be plugged into them?
• Is there room for MCX instead of MMCX for DI0/DI1? If MMCX is going to become Sinara's de-facto connector for places where SMA/BNC is too big then we should consider whether it's robust enough for use on a crate front panel. See also here.

[gkasprow]

this should fit

[cjbe]

@gkasprow according to ST's RM0433 section 59.4.1 the JTCK line has an internal ~40k pull-down that will fight with the 10k pull-up. If we are going to have a resistor it should be a pull-down.

[gkasprow]

switched input buffers to 5V-tolerant SN74LVC1G125DCKT fixed TCK pulldown resistor.

[hartytp]

:fireworks:

[cjbe]

@gkasprow could you make the following two changes:

• it would be useful if the P12V0A and N12V0A rails are brought out to the "ADC and DAC header" (instead of P/N13V0S).
• move the MMCX digital inputs to pads with timer capture-compare inputs. E.g. move DI1 and DI2 to PA3 and PA8.

[dtcallcock]

On the 'Stabilizer AUX connector' schematic page I don't see filter capacitors on ADC1IN1{P,N}. Also, the capacitor on ADC2_IN2_N (C164) looks like it has the wrong value.

This still seems wrong on v1.0 Production.

Also, I don't see the bidirectional buffers required for CPCIS & downstream EEM support. Is that still planned?

[gkasprow]

We finally decided not to implement downstream buffers due to limited use cases. But if you insist, I can add them.

[gkasprow]

@cjbe DI0 and DI1 are connected to ADC trigger lines. I can connect them in parallel to PA3 and PA8

[dtcallcock]

We finally decided not to implement downstream buffers due to limited use cases.

That's fine I just didn't see a consensus against it in the above thread so I wanted to check.

As @jordens mentioned, the killer app here is being able to do drive an Urukul and do phase/frequency servoing. However if an RF mezzanine for Stabilizer is thought to be a better way of doing it (as @hartytp suggests) then I'd be ok with leaving them off. I just don't want to be in a situation where one has to resort to adding a Kasli or Humpback just for want of a few LVDS buffers.

[gkasprow]

would assembly option be fine for you or you prefer a firmware-configurable direction control?

[gkasprow]

I could simply put additional buffers with reversed direction on the other side of PCB nad keep them DNP

[dtcallcock]

If that's easy for you to do, it sounds like a reasonable plan. These are easily hand-solderable SOIC-8 packages by the look of it.

[gkasprow]

OK, done

[gkasprow]

and drivers

[gkasprow]

they have nearly mirrored pin assignment so that was easy

[dtcallcock]

Looks good. Won't the receivers need some DNPed pads for 100Ohm termination though?

[gkasprow]

true, just added them:)

[cjbe]

@gkasprow Could you reconnect the P/N13VS to the "CPU ADC DAC header" (J13).

This way the piggyback board has access to the noisy but higher current P/N13VS from J13, the lower current nice supply P/N12VA from J4, and P12V0 and P3V3 from J3.

[cjbe]

@cjbe DI0 and DI1 are connected to ADC trigger lines. I can connect them in parallel to PA3 and PA8

This is fine. If we need more IO, we could remove the connection to the ADC trigger lines, as PA3 / PA8 give us the timer inputs - we can use this to timestamp the edges and trigger the ADC at a fixed time off-set from this.

[gkasprow]

I’m afraid it already was sent for production…

[cjbe]

No problem - this is a minor user-friendliness improvement we can add to the next revision