Closed gkasprow closed 5 years ago
Another option is to add yet another high speed connector for 200Mbit QSPI link
If you can find something wit the right stackup, what about replacing all three connectors we currently have with a single Samtec connector (something like a lower pin-count FMC)?
Or, hell, go the full way and just use FMCs. i.e. make two front-pannels for Stabilizer: one which is the standard 4HP FP, and one with is 8HP with an AFE mezzanine cutout. Then put an FMC (or similar connector with fewer pins) and route all analog/digital lines on to that.
That might actually work out nicer than the current design, since getting the stackup both electrically and mechanically reliable using separate FPs and pin headers can actually be a bit of a pain...
Thoughts?
going this way, we can reuse Sayma AFE form factor and connector signal assignment...
The issue with BGA connectors is that you cannot make such AFE at home...
@jordens what was your conclusion about all of this? What (if any) changes do you want to make for pounder?
I think there is a pounder issue for this.
Thanks for the link. Can someone more familiar with the microprocessor pin functions confirm what if any changes that requires to stabilizer please?
This is the last issue, so I’m keen to close ASAP and get v1.1 off to manufacture
I guess @gkasprow will propose those changes. Connect QUADSPI to the AUX header instead of the SPI1 bus that is connected now. Drop LPUART1_TX and PC8 and use those for the two additional QUADSPI data pins. After https://github.com/sinara-hw/Stabilizer/issues/13#issuecomment-528980208 it would then make sense to wire SPI1 to the EEM header instead of SPI6.
@jordens we need both SPI and QSPI. I will connect it instead of PD10 LPTIM1_OUT HRTIM_CHE1 HRTIM_CHE2 HRTIM_CHA1 HRTIM_CHA2
I can also choose other pins instead
Do we need both SPI and QSPI? I'd rather have timers available on the mezzanine.
We need SPI for attenuators in Pounder and QSPI for DDS. but, we can also connect it instead of LPUART1_TX PC0 PD10 PC8 UART4 Rx and one selected timer lines.
The QSPI lines have also some useful alternative functions: IO3
IO2
IO1
IO0
CLK
NSS
OK. UART is less useful for the mezzanine IMO. We also have another header for a uart. From my perspective either set of pins is fine.
I mean that we already have this UART line among QSPI lines :)
The header has the following pinout. I swapped IO order to make routing easier
update
Cool. Can you post a new rc pdf please?
Sure, let me finish the routing. I also added QSPI source termination.
Ok. But if people request final changes to the schematic don’t you want to hear them before you do the routing?
that pinout is fine from my perspective.
Consider routing QSPI to the extension connector instead of GPIO. Another option is to add yet another high speed connector for 200Mbit QSPI link