Closed jordens closed 3 years ago
can we do something with it in HW? Is this issue described in STM32 errata?
There was no erratum. Apart from the existing 50R series I don't see what could be done. Also we don't expect to do that many reads so for most applications this won't be critical.
The quadspi peripheral has a half clock cycle read contention bug (at least in the AD9959 use case).
Tracking https://github.com/quartiq/stabilizer/issues/101 here as well since it is likely a silicon hardware issue that would affect any firmware.