Closed marmeladapk closed 5 years ago
From @hartytp on 2017-11-07 20:30
@gkasprow Can you ship us all but 1 of the AD9910 Urukul prototypes you've ordered as soon as basic functionality/"no smoke" testing is complete (i.e. don't complete the above detailed testing first!).
Thanks!
From @hartytp on 2017-11-07 20:30
@gkasprow @jordens Feel free to add more tests to the above list.
From @hartytp on 2017-11-08 03:32
@gkasprow When you ship the AD9910 DDSs that we paid for, please can you ship one to @jordens?
From @jordens on 2017-11-08 08:47
Updated it a bit. Please ship right after smoke test:
We'll be happy to help with characterization afterwards.
From @hartytp on 2017-11-12 18:22
@gkasprow Is Urukul due to arrive this week? When it arrives, please can we prioritise no smoke/basic functionality testing (see reobert's list) above finishing Zotino -- I'd like to get Urukul prototypes shipped asap. No need to do the detailed testing for now.
Thanks!
From @gkasprow on 2017-11-12 18:26
@hartytp OK, 2 Zotinos + BNC adapters were shipped on Friday. Once I receive DDS, I will test them ASAP.
From @hartytp on 2017-11-12 18:27
Thanks!
From @gkasprow on 2017-11-12 18:32
@hartytp There are no panels for DAC BNC adapters attached - I forgotten about them. Will ship them next time with some other stuff.
From @hartytp on 2017-11-12 18:43
@gkasprow No problem. That can wait.
If there is any time before Urukul arrives, it'd be great to get a few of the analog test for Zotino done.
From @gkasprow on 2017-11-12 19:04
@hartytp Sure, once I repair my bard, will continue with measurements.
From @hartytp on 2017-11-12 19:23
Great, thanks @gkasprow!
From @jordens on 2017-11-19 16:38
@hartytp could you remember to do a bit of triage on the issues you file (i.e. assignee, labels, milestone)?
From @hartytp on 2017-11-19 18:48
sure
From @hartytp on 2017-11-20 18:55
@gkasprow For the current source biasing, my inclination is to go for Daniel's suggestion of the LT3092. They're pretty cheap ($2 in quantity) and seem like a better/easier solution than building our own current source.
@jordens @gkasprow if you're oaky with this approach, then we should buy an eval board at some point and test this out with the v1.0 boards we have. I'm happy to do this testing if that helps -- I probably won't do this until after Christmas, but I don't think we're in a rush for it.
From @jordens on 2017-12-11 18:24
@a-shafir and I will take care of the first round of noise, power, RF switch testing.
From @hartytp on 2017-12-11 18:26
Cool.
Out of curiosity, do you have a proper phase noise/amplitude noise meter? Or, will you just stick this on a spectrum analyser?
From @jordens on 2017-12-11 19:16
We have proper tools.
@gkasprow how are the AD9912 variant boards?
From @gkasprow on 2017-12-11 21:11
@jordens I have them all in my lab but was busy with Sayma Ethernet debugging. You can follow my fight here
From @gkasprow on 2017-12-11 21:12
So the next thing is 9912 testing.
From @jordens on 2017-12-11 22:32
I am following that and involved. Thanks for the AD9912 update. Once you have smoke-tested them like the AD9910 stuff, you can send two of them to me.
From @a-shafir on 2017-12-11 22:45
@gkasprow what was actually flashed into the CPLD on the 9910 board we have in Berlin?
I see 2 options https://github.com/m-labs/sinara/tree/master/ARTIQ_ALTIUM/EEMs/Urukul/CPLD_code or https://github.com/quartiq/urukul
I am testing h/w but can't generate any output on the IO_SESET (P129) and some pins around.
From @a-shafir on 2017-12-11 23:02
@gkasprow how you tested 3U DDS 9910? Have you got DDS ic working? Do you have the code that sent the spi commands, what actually sent to DDS/atten etc?
From @gkasprow on 2017-12-11 23:02
@a-shafir I burned Roberts Verilog code. The only change I did was assignment of test points. Now we have:
assign tp = (cfg_data_rst | ((~en_9910) & tstriple7_i));
assign tp_1 = dds_cs_n;
assign tp_2 = dds_sck;
assign tp_3 = dds_sdi;
assign tp_4 = dds_io_update;
From @gkasprow on 2017-12-11 23:05
I connected 9910 devkit via DIO-Tester module to make sure that Robert's code works. In this way I could communicate with it using LVTTL signals
From @gkasprow on 2017-12-11 23:06
I also modified the verilog code so all 4 channels were active simultaneously. In this way I tested if PLLs are locked. Here is the code: Urukul_CPLD_all_ch.zip
From @gkasprow on 2017-12-11 23:08
To do general purpose communication over SPI I use little Artix 7 devkit with USB and FORTH processor that translates UART commands to bit-bang protocol, i.e. SPI. It works really fast but it's written in FORTH, so probably not really useful for you :)
From @a-shafir on 2017-12-11 23:13
@gkasprow i see io_reset commented in the code. probably some other changes. Please also attach the pin assignment for the code. So what was generating the DDS SPI command? 9910 devkit? I have no devkit. Can you generate a dump (sequence) of the commands? Also what about the reading from DDS when all in parallel?
From @a-shafir on 2017-12-11 23:15
@gkasprow i see why in_sel not working to - it commented out Good that i got this data from you )
From @gkasprow on 2017-12-11 23:19
The original DDS was working in parallel. So I didn't read the status from externally connected ones. You can compare this code with one @jordens posted. I did not touch the pins assignment. My CPLD project is here
From @gkasprow on 2017-12-11 23:21
This is how typical setup with devkit looks like. I this case I connected Sampler module, but the idea is same.
From @gkasprow on 2017-12-11 23:24
this is the FORTH code I use to talk to LV595 registers. The FORTH ascii is executed in FPGA and is toggling IOs routed to an IO register with a few MHz rate. CPU runs with 50MHz clock. The function below writes 16 bits via SPI to the register and reads them back.
: spi_LV595 ( a )
1 OUT0_SET_REG io! \ SCK hi
1 16 lshift OUT0_SET_REG io! \ OE buff active
1 2 lshift OUT0_CLR_REG io! \ RCLK low
16 0 do
dup
1 15 lshift and
if
1 1 lshift OUT0_SET_REG io!
else
1 1 lshift OUT0_CLR_REG io!
then
1 OUT0_CLR_REG io! \ SCK low
2*
INP0_REG io@ 4 rshift 1 and +
1 OUT0_SET_REG io! \ SCK hi
loop
1 2 lshift OUT0_SET_REG io! \ RCLK high
1 2 lshift OUT0_CLR_REG io! \ RCLK low
1 16 lshift OUT0_CLR_REG io! \ OE buff inactive
$ffffff and \ return only valid bits
;
From @gkasprow on 2017-12-11 23:32
@a-shafir you are right - I had to modify the reset pin state to make it working.
From @gkasprow on 2017-12-11 23:34
And the code you have burned in your CPLD is in Urukul_CPLD_1ch.v file
From @gkasprow on 2017-12-12 16:51
@jordens here is your 9912 :)
From @jordens on 2017-12-12 16:56
@gkasprow Nice! Other than the missing amplifier, are there any other issues? Is the solder on the underside bad as well?
From @hartytp on 2017-12-12 16:59
Nice!
From @gkasprow on 2017-12-12 17:03
I got this amp separately. The PN is wrong so they got ones with straight leads and had to replace them. It seems that the ICs they got had problems with wetting because other chips are fine. Anyway, it's their responsibility to solder it right
From @jordens on 2017-12-12 17:15
Are you returning the AD9912 boards to Technosystem to be fixed as well?
From @gkasprow on 2017-12-12 18:06
I will fix one piece myself to test it. Rest of the boards will be returned. I talked with the company and they say that it is quite standard thing that some chips have poor wetting and side contacts are not always covered by the tin. The flux that is part of the soldering paste is only roughly 10..15% of it and is not always able to clean the contact side. The joint still maintains the contact because it is low side of it which does the job. Side area does not need to be covered, but if we want, they can fix it.
From @jordens on 2017-12-13 08:47
IMHO it is likely that the joints are bad on the underside as well if they fail to wet that dramatically on the edge. And since they probably didn't inspect those joints there is no telling. I'd like to see them fix it.
From @gkasprow on 2017-12-13 09:09
I just desoldered the chip and the bottom pads are correctly soldered. Anyway it just looks non professional and should be fixed.
From @a-shafir on 2017-12-13 10:42
This is a long known for the technologists that too much solder is not helping and even can cover some problem. But in this case it is not about the professionalism but about Optical inspection standards. All the packages designed that way that there is possibility to ensure by inspection the proper electrically and mechanically soldering. For this package there must be wetting on the side edges of the pads. This indicates that there is wetting under the pads and also improves mechanical properties.
For some of the packages we have (BGA and some of the qfn with signal pads under) the OIS will not enough. I think need to check if the factory can do x-ray inspection, they must have it in or out house at least for BGA but also for some regulator chips etc. Visual inspection of the QFN etc is the must. It shall not increase the cost of the samples production more than few %
Any way investing our time to solving the technological issues is the worst case scenario.
From @a-shafir on 2017-12-13 12:50
Urukul 9910, 4th channel, 10.000MHz, variable attenuation test, no termination:
From @gkasprow on 2017-12-13 13:29
@a-shafir look here
From @a-shafir on 2017-12-13 13:40
@gkasprow ok, this is a news for me too. There are 3 similar looking "QFN-style" packages:
That minds for us:
From @a-shafir on 2017-12-18 00:41
Gateware, core drivers and experiment for Urukul AD9910 rev 1.0 board.
The current setup is for KC705, see the details here: https://github.com/m-labs/artiq/commit/dd3c8a336dc12cda33cadebdf3bafc77c0bc1565
The experiment initializes FMC DIO, the Urukul board and configures the single tone for all 4 channels. Attenuator and SW are supported.
There are 2 "interference generator loops" (for DDS3 SPI and for ATT SPI). Each can be activated in the experiment. Note: with the current RTIO gateware it is not possible to generate the NU-mode intensive SPI communication so if any interference from the SPI clock will be seen on the output it will be not the worst case scenario.
The 4-channels DDS output:
The setup:
From @jordens on 2017-12-18 17:40
More data and screenshots to follow.
From @dhslichter on 2017-12-18 18:53
@a-shafir why are you using scope probes to look at the DDS outputs instead of SMA cables?
From @gkasprow on 2017-12-18 19:01
@jordens in such setup you easily receive and induce current from every short wave radio station including CB :)
From @jordens on 2017-12-18 19:57
@gkasprow in general yes, but not if you are in a room that is as insanely shielded as the one we are doing the tests in ;)
From @hartytp on 2017-11-07 20:29
Use some fixed reference frequency for all tests, such as 80MHz.