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sinara-hw / Urukul

4 channel 1GS/s DDS (AD9910 or AD9912 variant)
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redo CPLD wiring #30

Closed jordens closed 5 years ago

jordens commented 5 years ago

Redo the CPLD wiring to avoid pitfalls, decouple the channels, remove hidden state, and improve interoperability with the different software modes.

Compensate pin usage (+25) with (up to -35 available):

tballance commented 5 years ago

+1 for pinning out the profile pins. This would be really useful for us. When the CPLD code is being revisited, I think it would also be useful to add more detailed version and build info which can be read out through the SPI interface.

gkasprow commented 5 years ago

we can also use a bigger BGA256 package and route all pins without any compromises. Don't we want more CPLD resources?

jordens commented 5 years ago

Right. A small fpga with lvds would make the 4 lvds cmos converters redundant as well. Might be worth it.

gkasprow commented 5 years ago

FPGAs have usually much higher pin to pin delays than CPLDs and higher jitter. And it is much more complex modification than just replacement of the CPLD.

jordens commented 5 years ago

Sure. Just pointing out the option. A BGA CPLD with a bit more resources would be nice to alleviate the pin and resource constraints.

tballance commented 5 years ago

From a control perspective, it seems to me that it would be nice to expand the CPLD shift register to include some bits for addressing. This would allow us to read out more detailed version info (like a human-readable build string) and also expand the ability to operate in different modes. A mode that could be useful for us would allow us to control the profile pin switches from a fifo in the CPLD which is programmed through SPI writes and clocked out with a strobe pulse from the EEM interface. This would enable us to make bursts of fast switches (<1us) between profiles which would not be achievable through SPI writes alone. Also nice would be to have the CPLD interface backwards compatible, in that it boots in 'legacy mode' and can be switched (through a write sequence) to the expanded mode if the proto_rev version is above a threshold. From a user perspective I think this would be nice, as many people will have mixed hardware and making it 'plug-and-play' will hopefully reduce the number of issues about hardware not working.

gkasprow commented 5 years ago

@jordens do you think adding I2C to SPI -> JTAG converter would be useful as it is in case of the Banker?

jordens commented 5 years ago

To jtag the cpld over i2c? Probably not that high value in practice. And part of the tooling is missing.

gkasprow commented 5 years ago

@jordens please review the CPLD signal assignments https://github.com/sinara-hw/Urukul/releases/tag/v1.4rc1

jordens commented 5 years ago

I'm on vacation until the end of the week. Will review then.

jordens commented 5 years ago

@tballance These are all nice ideas. Some of them is (like the multiple registers and the addressable SPI switch) is planned/implemented in Mirny and looking for funding (https://github.com/quartiq/mirny/issues/1). The same would apply to these features and the gateware/software for Urukul v1.4.

jordens commented 5 years ago

@gkasprow I looked at the schematic and ported the current gateware.

gkasprow commented 5 years ago

done