Problems with channel 0 synchronization

[marmeladapk]

6 attenuator SPI lines run under PLL filter of AD9910 in channel 0:

• ATT_S_OUT0
• ATT_S_IN1
• ATT_S_OUT1
• ATT_S_OUT2
• ATT_LE2
• ATT_S_IN2

These lines seem to have a significant enough effect on PLL filter that it causes SMP ERR to appear and sometimes even phase glitches in output signal (caused by ATT_S_IN2).

To fix this,

• these lines must be rerouted away from loop filter and P1V8_CLK_VDDA (maybe even away from DDS0 if it's possible)
• stackup issues must be fixed (https://github.com/sinara-hw/Urukul/issues/72)
• as well as these signals should have a proper continuous reference plane.

More info can be found in https://github.com/m-labs/artiq/issues/1692.

[gkasprow]

fixed in v1.5.5

[marmeladapk]

I'd say that these lines should be rerouted away from P1V8_CLK_VDDA under AD9912 as well.

Is it possible or worth it to fight for continuous reference plane for these signals?

[gkasprow]

I think we can do it

[gkasprow]

I did what I could

[dnadlinger]

Given that the PLL nodes are apparently more susceptible than anticipated, I suppose it might be interesting to see whether toggling all the potential agressor lines as aggressively as possible leads to phase noise on the output even after the fix. (Fixing the huge return current loop is bound to improve this a lot, though!)

We typically leave all the attenuators untouched for virtually all channels, though, so it's not a huge issue for use in the experiments here.