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sinara-hw / Urukul

4 channel 1GS/s DDS (AD9910 or AD9912 variant)
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CPLD XC2C256-6FTG256C is EOL #82

Open MorganTL opened 1 month ago

gkasprow commented 1 month ago

any suggestion what family we could use here?

Spaqin commented 1 month ago

Mirny uses the same CPLD.

A suggestion would be to use Artix-7, like XC7A35TICSG324 or XC7A100TCSG324, depending if 35k logic cells would be fine or we need 100k.

gkasprow commented 1 month ago

Artix is FPGA, which means it has much higher internal delays and is suitable for synchronous designs. CPLD was placed here as a simple asynchronous glue logic. Such a big FPGA would significantly increase the board cost because we also need extra power rails.

gkasprow commented 1 month ago

Since AMD and Lattice do not make any CPLDs anymore, we can move to Cypres or Altera: 5M2210ZF256I5N EPM570F256C4N CY37256VP256-100BGC

@jordens Maybe the ICE40 family could be fine here?

jordens commented 1 month ago

That would be interesting to explore.

kaolpr commented 2 weeks ago

If there are no pending ideas on implementing some more elaborate logic we could go with iCE40 HX8K as in Fastino. This would let us drop LVDS transceivers too (same for Mirny).

dnadlinger commented 2 weeks ago

The biggest (in relative terms) design we currently need is the status readback for SUServo mode: https://github.com/quartiq/urukul/pull/11. For this, we ran right up against the size limits of the parts that were on older revisions, at least in a straightforward implementation, though there is some discussion on how to best implement this in a glitch-free way still unresolved (see linked PR).

dnadlinger commented 2 weeks ago

(the amount of logic required is still very small; I suppose you could just run that PR through the iCE toolchain to check)