WR oscillator Si549 characterisation

[WeiDaZhang]

The thermal character of the DCXO Si549 we use in WR implementation has drawn our attention. It has been noticed the open-loop phase noise of the DCXO changes over different (thermal) environments. More precisely, the phase noise slopes and interception points between slopes changes in the very close-in region 1Hz and sub 1Hz, when the thermal environment changes. These frequency regions are not specified in its datasheet.

Oven tests suggest pure temperature does not make a big difference even in 20C changes. However, changes of airflow rate make obvious differences. Heat sinks attached to the DCXO make close-in noise less relative to the airflow (or thermal environment), presumably because of added thermal mass.

The test PCB is not designed to strengthen the thermal grounding of the DCXO particularly. The result suggests heavy coppering the area and vias are necessary, and potentially heat-sink mounting.

In general, PLL removes the close-in noise of a VCO. However, if the slope is steeper than f^-3, careful design of loop filters is required.

[WeiDaZhang]

Also, IIRC you tried both the CPLL and QPLL. Conclusion was that both add about the same level of noise, so it's good to minimize the number of PLLs, but no particular recommendation for optimizing the noise was found.

The conclusion of QPLL and CPLL are more or less the same was not involving CDR, not a real use case, not a remote link. I'll have to check this. The recommendation is, however, Xilinx automatically add an MMCM PLL after Rx CLK, this one is not good for reducing phase noise or instability.

[WeiDaZhang]

Interestingly in the second article, a DFF is used at the output of FPGA generated 10MHz to improve the performance.

Can you clarify what this means? IIRC you had a nice BD of this.

[Reference: White rabbit switch performance in grandmaster mode]

[hartytp]

Thanks @WeiDaZhang !

[WeiDaZhang]

@mattiarizzi Hello We have been analyzing our results against a few papers and reports of yours. They have been very helpful. There is a bit unclear to us, and I'm wondering if you could provide some hints

In [White Rabbit Clock Synchronization: Ultimate Limits on Close-In Phase Noise and Short-Term Stability Due to FPGA Implementation], Chapter VII Fig. 18, 20dB improvement is gained by the LJD from the "Standard Setup". The LJD results basically reached GTX limits in Fig. 14 and DDMTD limits in Fig. 8.

Is this 20dB mainly benefited by "using an external board to perform a clock synthesis currently done inside the FPGA" as mentioned in [White Rabbit Switch performance in Grandmaster mode]?

Generally speaking, avoiding using MMCMs or PLLs in FPGA, and replacing the frequency synthesis module by external PLLs provide the improvement. Is this what you mean? Thanks.

[mattiarizzi]

Hello, sorry for the delay, tomorrow morning I will reply to @hartyp and @WeiDaZhang

[WeiDaZhang]

@mattiarizzi no problem

[mattiarizzi]

(Si549) It's extremely stable -- look at the data we've posted! What's the temp co of the VCXO you're using, and how does it compare to the Si549 anyway?

Yes, it is. That's a good news. The VCTCXO mounted on WRS are more unstable (at ADEV = 1s) in free-running mode, due to the temperature compensation circuit.

Yes, Fig. 10 in [1], Fig. 8 and Fig. 18 in [2] suggests the additive noise or the DDMTD floor is ~-105dBc/Hz @10MHz, which is similar to our ~-90dBc/Hz @125MHz

Yes, it is -105 dBc/Hz from 10Hz to a few kHz (10 MHz carrier).

(2) corresponding to satellite mode noise. The CERN results seem not very consistent (probably because I didn't understand fully), in Fig. 18 in [2] it is around -85dBc/Hz, but in Fig. 3.10 in [3], it seems about -105dBc/Hz. I need to carefully read again to tell.

It's consistent. The -85dBc/hz is the DDMTD noise floor with a STANDARD WRS in Grandmaster mode. The STANDARD in Grandmaster mode use a MMCM to multiply the external 10MHz input ref clock, this MMCM has a lot of phase noise between 100kHz-1MHz. This phase noise is aliased into the DDMTD baseband because DDMTD is a sampled system. See https://white-rabbit.web.cern.ch/documents/White_Rabbit_Clock_Characteristics.pdf and https://www.ohwr.org/project/wr-low-jitter/wikis/Documents/White-Rabbit-Switch-performance-in-Grandmaster-mode for more info

Generally speaking, avoiding using MMCMs or PLLs in FPGA, and replacing the frequency synthesis module by external PLLs provide the improvement. Is this what you mean? Thanks.

Yes. Avoid MMCM at all cost, in Virtex-6 they are implemented as delay locked loops, very noisy at high frequency offset

Interestingly in the second article, a DFF is used at the output of FPGA generated 10MHz to improve the performance.

The DFF is mounted in any WRS, the DFF does not introduce more phase noise than what you find inside the board (this statement is valid from sub-hz to 100kHz).

About the DDMTD white PM noise floor: you can improve it with multiple DDMTDs inside the FPGA. Check https://www.ohwr.org/project/wr-low-jitter/wikis/Documents/DDMTD-report page 36, figure 36 However you cannot improve the flicker noise because it is introduced by the input clock buffers.

About Si549: the closed loop results are very interesting. Are you updating it at 7 kHz or with a downsampled signal?

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[jordens]

The aliasing in DMTD (both digital and analog) can be really nasty. It makes masers at NIST look worse than they are because it doesn't properly reject minor high frequency "issues".

[WeiDaZhang]

@mattiarizzi Thanks. I see. When DDMTD samples the MMCM output significant noise is aliased back.

[WeiDaZhang]

A few more characterizing tests were done on "Remote" link with temperature-controlled environment. Result suggests working temperature has an observable impact on MGT-WR-PLL implementation stability. 45~55 degrees C oven temperature change causes 6e-14s ~ 9e-14s @ 1s variation on modified Allan deviation (curves with square marks).

Another experiment confirms external D-FF (DDMTD input register) doesn't help to improve stability in the "remote" link setup. We are limited by CDR noise floor (white) and CDR flicker noise (f^-1).

[hartytp]

We now have all the data I think we could possibly want for the prototypes.