Open gkasprow opened 3 years ago
It's a lot of ADC channels... but maybe the metrology people are interested. Would be interesting to see what the common mode and channel-to-channel aperture jitter are. FADE looks interesting though.
No immediate applications for that kind of multi-channel ADC come to mind for me, unfortunately.
One could potentially couple multi-cell photodiodes (i.e. from Hamamatsu) to detect a qubit state with a very low latency of just a few clock cycles...
but for this, you're probably better off with a comparator per channel plus a digital input. ADC means a lot of heavy data lifting.
Btw, here is a public repo of the project and issue describing how ADC data are handled with ARTIQ https://github.com/elhep/MCORD_DAQ_Firmware/issues/5
We decided to go for an FMC and reuse existing FMC carriers. Each FMC will contain 128 ADCs working at 50MS/s@10bit or 40MS/s @12bit. It can also work in 64-channels mode with 100MS/s@10bit or 80MS/s@12bit
How many ADCs will be on a single FMC? Have you estimated what energy will be dissipated and if it can fit in FMC spcs on current?
I'm designing a 3072-channel data acquisition system for X-ray diagnostics of thermonuclear reactors (ITER and similar). The DAQ will acquire signals from Gas Electron Multiplier. We plan to use ZynQ US+ modules from Trenz with integrated 32-channel AFE chips from Texas. First tests using EV kits showed that the approach is feasible, it's possible to use DC-coupling as well. The system will use ARTIQ for synchronization, diagnostics, triggering, slow-control, and configuration. It is missing a high-speed low latency data channel.
It's already the second project for HEP and plasma physics where we will use ARTIQ outside of quantum physics. Both require high-speed low latency transfer of massive amounts of data. Low latency means hundreds of ns.
The first one is MCORD for which we built the 16-channel ADC+TDC ; it will use MTCA, AFCKU carrier, and modified Metlino. The low latency channel will be built using two IOSERDES blocks routed to the remaining fat pipe lanes.
The second project will be based on the 3U form-factor where every 3U module will support 128 analog channels built with TI AFE chips mentioned above. We have much more data so multi-lane 10Gbit Ethernet and probably the open-source FADE protocol will be used to connect it to the CPU farm. The Ethernet will be used for slow control and diagnostics, as in the previous case.
I have two questions: