Mirny schematics review

CannaCardo commented 6 years ago

I sketched initial version of schematics (link). I've chosen ADF4351 (HMC833 has higher price and twice the power consumtion). I left EEM connectors since I'm not sure which alternative (PoE/ I2C from Kasli and 12V from somewhere/ something else) would be better. Also I've left out frequency multipliers for now. I understand that this section should be realized as separate microwave PCB and it can be designed separately. I couldn't find any off-the-shelf 40MHz-4GHz multipliers, so that would mean designing it from the beginning or perhaps using a lower bandwidth doubler/tripler? I appreciate any suggestions and having my mistakes corrected.

hartytp commented 5 years ago

@gkasprow I agree. Expose the RF and DIO on sensible connectors and add some mounting holes.

CannaCardo commented 5 years ago

Should the IDC be made incompatible with EEM connector to avoid possible confusion? Or would clear silkscreen be enough to shave additional BOM line?

hartytp commented 5 years ago

Should the IDC be made incompatible with EEM connector to avoid possible confusion? Or would clear silkscreen be enough to shave additional BOM line?

Yes! cf what we did on stabilizer.

I'd try to position the IDC so that it can either be used as a board-board header for a long mezzanine card (a la Stabilizer) or used with a ribbon cable for a shorter mezzanine (as Greg suggested above). Basically, kick this decision into the long grass.

jordens commented 5 years ago

I'd still put that mezzanine IDC to the right of the PLLs, out of the RF zone, either near the top or near the bottom to not interfere too much with the center area. Could also be horizontal instead of vertical. Also not to far to the right to not interfere with the cPCI S.0 adapter.

Keep the board at 160 mm for now. Move the EEM IDC connector to the designated place (for the cPCI S.0 adapter board, see the other recent designs of @gkasprow ) If (a) it is really easy and (b) does not interfere with the EEM connector position, (but only if both are met) add the cPCI S.0 connector but DNP it.

gkasprow commented 5 years ago

simply copy position of the EEM connector from Stabilizer. Take into account that CPCIS adapter will have two connectors for double EEM boards so make some space as I did on the Stabilizer board.

CannaCardo commented 5 years ago

IDC used in Stabilizer is 16pin, currently we have 28 DIO lines, I2C and 5 voltage rails (-5.5, +3.3, +5.5, +7.5, +12) supplied to mezzanines. Assuming we keep all rails and take 2 pins for ground (which imo would be on the short side) that leaves 9 pins for DIO and I2C. We could either

leave it as it is if that's ok,
drop some power rails/DIO for ground (I'd say 7 DIO lines would be enough for SPI+driving 4 switches or something similar, traces could be matched in length),
add 2nd IDC connector/ pick larger one.

cPCI S.0 connector would interfere with bottom mounting hole for adapter and EEM connector.

gkasprow commented 5 years ago

we will use 220mm CPCIS boards anyway, just use holes and IDC connectors placement as in Stabilizer.

CannaCardo commented 5 years ago

MCX/MMCX connectors work up to 6GHz (see), if we want to pass up to 12.8 GHz to AFE board we need to pick something different, I've left SMPs for now.

EEM connector moved and mounting holes added for CPCIS adapter,
AFE connector changed to IDC,
SMAs changed to angled ones,
lightpipes dropped since they're no longer needed,
0R resistors added to tie SMAs and panel to ground like in Urukul,

CannaCardo commented 5 years ago

I've rerun the DC drop analysis and did the thermal simulation. The environment setup: temp_env Results: temp@flow_50 Same conditions but flow rate at 130cm/s: temp@flow_130 Thermal cutoff would be at about 15cm/s flow rate (IC12 at 80deg): temp@flow_15

gkasprow commented 5 years ago

What power dissipation did you assume for the power stage and PLL chip?

jordens commented 5 years ago

@CannaCardo thanks

[x] Make sure that C42 (all four) meet the minimum bypass requirements for the LDO. Maybe just increase them to 2.2 µF or similar.
[x] With the benefit of hindsight we should split up the attenuator daisy chain and route CS, SDI, SDO per attenuator to the CPLD. If it helps with routing/wiring CLK can stay common.
[x] I would like to see more IO to the mezzanine. At least 8.
[x] Now that this board has become simpler, is there any chance to make it 4 layers? Getting rid of the lower ground layer and merging the last two bottom layers seems decidedly possible.

hartytp commented 5 years ago

@CannaCardo can you confirm which PLL IC you're planning to use? Is it the ADF5356?

Also, we should consider adding the pads for a (DNPd) active (3rd order) loop filter.

CannaCardo commented 5 years ago

What power dissipation did you assume for the power stage and PLL chip?

I've used power consumption values with AFE at full load:

IC1	0,65 W
IC2	0,6 W
IC6	0,65 W
IC7	0,32 W
IC9	1 W
IC10	0,33 W
IC11	0,2 W
IC13	0,8 W
IC15	1,32 W
IC16	1,2 W
IC17	0,46 W
IC20	0,17 W
IC21	0,17 W
IC22	0,15 W

Make sure that C42 (all four) meet the minimum bypass requirements for the LDO. Maybe just increase them to 2.2 µF or similar.

Ack

I would like to see more IO to the mezzanine. At least 8.

Would it be ok to use 18pin or 20pin IDC connector then? Seems like the easiest solution without any drawbacks

@CannaCardo can you confirm which PLL IC you're planning to use? Is it the ADF5356?

Since there aren't really any plans for AFE board, I'd say that ADF4355 or ADF4356 would be better. ADF4356 seems like a best pick since noise-wise its better than ADF4355 and is identical to ADF5356.

jordens commented 5 years ago

The users are specifically interested in frequencies around 6.8 GHz. They'll handle the AFE. Let's stick with the ADF535[56]. I don't think the price difference should decide that. Maintaining variants and the induced board shortages would more than make up for that. Yes. just a bigger IDC is fine. Also, and again, I think the negative supply can really go away. That can be implemented on the AFE.

CannaCardo commented 5 years ago

ADF535[56] RFoutB frequency range is 6.8 - 13.6 GHz (doubled VCO frequency) and RFoutA range is 53.125 MHz - 6.8 GHz (VCO divided by 1,2,4,8,16,32 or 64). With current AFE components there's a gap in 4 - 6.8GHz range.

gkasprow commented 5 years ago

Guys, we have to converge quickly to the production version of the board. @CannaCardo has to finish writing his thesis and needs working HW and tests done. So let's leave minor tweaks for the second revision and proceed ASAP.

jordens commented 5 years ago

The gap Is fine. People will need to tweak the rfouta path, or use the non doubled pll chips and a custom.afe.

jordens commented 5 years ago

Imo there are only small things left (split attenuator spi, four layers, more Dio on mezzanine connector). See above. Some of them already mentioned a while ago.

CannaCardo commented 5 years ago

Ok, I've updated schematic & pcb:

changed to 4 layer stackup (updated DC Drop Analysis )
N5V5 supply removed
AFE DIO increased to 8
attenuators SPI is separated
ADF4355 changed to ADF5356 as default
added variants for other ADF chips

jordens commented 5 years ago

Excellent! Two things I'd like to sneak in, then I'll shut up.

[x] Let's populate the AFE IDC connector and the power supply bypassing/filtering components there by default.
[x] The I2C switch can go. It's a single mezzanine now. Just connect the mezzanine, the eeprom and the temperature sensor directly. The mezzanine can figure out how to organize its address space without colliding with the Mirny temp sensor, eeprom and two levels of upstream switches.

CannaCardo commented 5 years ago

Done and done.

jordens commented 5 years ago

Good catch on the EEM0 global clock pin! Nothing further from me.

jordens commented 5 years ago

When you add the release assets, put the fabrication data (BOM, Gerbers, placement, drill, variants, stackup, etc) into the ZIP. But post the PDF separately (and not in the ZIP).

gkasprow commented 5 years ago

@CannaCardo Please use OutJob file from Urukul project to generate the production documentation.

CannaCardo commented 5 years ago

Ack, I've uploaded fabrication files

gkasprow commented 5 years ago

for some reason the assembly house didn't know which chip to mount. I confirmed ADF5356

hartytp commented 4 years ago

@CannaCardo AFAICT this issue is complete (as the design has already been sent to production). Can we close?

sinara-hw / mirny

Mirny schematics review #1