timeline WUT hardware 0.1 -> 0.2 -> 1.0

[jbqubit]

In #97 @hartytp asks

Assuming we don't find any major mistakes in the prototype hardware, when do you think a second hardware order will take place? This will affect how much prototype hardware we buy.

• [x] @gkasprow Please predict date when the BOM and layout will be frozen.

• [x] @sbourdeauducq Please comment on status of ARTIQ support for Sinara hardware.

v0.1

From date order is placed with board house...

• 2 weeks for printing, stuffing (assuming 100% BOM availability)
• 1 week for WUT PCB checks using existing test tools (no ARTIQ dependence)
• 1 week for international shipping
• 3 weeks for testing, thrashing, bug busting, discussions by end users and M-Labs (@jordens visits JQI for a week)
• 2 weeks schematic update, layout fixes, repeat SI analysis

if v0.2

The need for a second prototype round will be decided for each PCB. From date order is placed with board house...

• 2 weeks for printing, stuffing
• 1 week for WUT PCB checks
• 1 week for international shipping
• 2 weeks for testing, thrashing, bug busting, discussions
• 1 weeks schematic update, layout fixes, repeat SI analysis

v1.0

Design locked in... purchases are placed with board house (eg technosystem.pl)

• 4 weeks slack for procurement spool-up by prospective customers
• 2 weeks for printing, stuffing
• 1 week for WUT PCB checks
• 1 week for international shipping

If v0.1 is frozen 1/1/2017 and you believe this timeline...

• one prototype round (v1.1) on the way to delivery of v1.0 4/7/2017
• two prototype rounds (v0.1 -> v0.2) on the way to delivery of v1.0 6/1/2017

• [x] @gkasprow Please comment on how realistic this progression is in your experience.

deprecate prototype hardware?

Depending on the type and severity of errors in prototypes it may be expedient to deprecate v0.1/v0.2 once v1.0 becomes available. If the deltas are just loop-filter components and phase-noise motivated layout tweaks I guess extended support of prototype hardware by M-Labs isn't onerous. If substantial monkeying is needed to get the prototype hardware to function at all (eg lots of flying leads, hacks to compensate for cross talk induced bit errors) deprecation may be in order. But this is speculation at this point.

[sbourdeauducq]

• 1 week for WUT PCB checks using existing test tools (no ARTIQ dependence)

@gkasprow what is your plan for the test suite? There is also the option of keeping this initial WUT testing to a minimum (power supplies OK, check that the FPGA answers to JTAG) for v0.1, until a proper test suite is developed and used for v0.2+.

[gkasprow]

@sbourdeauducq It is good idea. Wojciech is still occupied with another project so at the moment he cannot fully switch to test suite development. The plan was to at least check the SDRAM and transceivers and we should manage to do so. We can leave full connectivity checking for v0.2 when complete test suite is ready.

[gkasprow]

To mitigate the risk, we can assemble only 2 pieces of Metlino/Sayma AMC to check if no critical issues are present and within a few days assemble rest of them. Initial batch count was just 2 pieces but now it grown to higher volume. In case of serious PCB bugs we won't loose precious components but only PCBs.

[sbourdeauducq]

Right now there is mostly no ARTIQ support specifically for the new hardware. We have been busy with the PDQ, SAWG and DRTIO, and https://github.com/m-labs/artiq/issues/637 has been a frustrating time sink.

The major steps for something interesting (stand-alone Sayma) are:

• Kintex Ultrascale support in OpenOCD, done using KCU105.
• GTH port of the JESD204 core, @enjoy-digital will be working on it, can be done with the KCU105.
• DDR3, not started, needs hardware to test as KCU105 uses DDR4.
• support for the RTM FPGA, not started, preferably tested with new hardware but KCU105 can be reasonably hooked to KC705 for testing parts of it. needs hardware.
• getting the clock chips to behave, needs hardware.

[jbqubit]

To mitigate the risk, we can assemble only 2 pieces of Metlino/Sayma AMC to check if no critical issues are present

I like this approach.

We can leave full connectivity checking for v0.2 when complete test suite is ready.

We shouldn't migrate from v0.1 until all component connectivity is confirmed. Exception is if there's a serious bug in FGPA, SDRAM, clocking or transceivers that precludes such a check.

Right now there is mostly no ARTIQ support specifically for the new hardware. We have been busy with the PDQ, SAWG and DRTIO, and m-labs/artiq#637 has been a frustrating time sink.

Wojciech is still occupied with another project so at the moment he cannot fully switch to test suite development. Right now there is mostly no ARTIQ support specifically for the new hardware.

Both these answers are helpful in knowing the current state of development. More is needed to answer @hartytp question. @sbourdeauducq @gkasprow Please prognosticate about the timeline for development of tools to test

• [x] connectivity of all PCB components
• [x] data integrity at full data rate
• [x] operation of all PCB components sufficient to permit start of analog testing

[gkasprow]

Production test suite and verification of connectivity are two different things. We can check connectivity manually, line by line and in the meantime develop the production test suite.

[jbqubit]

From today's teleconference.

@gkasprow Confirms that BOMs are frozen for all the Sinara components slated for delivery with v0.1 #97. Does this mean

@gkasprow says to adjust timeline as follows to be conservative

• printing, stuffing (assuming 100% BOM availability): 2 weeks -> 3 weeks
• WUT PCB checks using existing test tools: 1 week -> 2 weeks

Consensus is that the following is too vague; specific tests must be defined. "3 weeks for testing, thrashing, bug busting, discussions by end users and M-Labs". Discussion goes on here #117.

M-Labs points out that most analog tests won't be practical until @sbourdeauducq "major steps for something interesting" are accomplished. @jordens predicts 6-8 weeks from today.

@jordens can just as well write gateware in Germany. Delay visit to JQI until analog tests are underway.

---

Updated timeline in view of today's discussion.

v0.1

Assume PCB order is placed with board house 1/1/2017.

• 3 weeks for printing, stuffing (assuming 100% BOM availability)
• 2 weeks for WUT PCB checks using existing test tools (no ARTIQ dependence)
  • power electronics test, DDR test, GTX transceiver test
• 1 week for international shipping
• 3-6 weeks for testing, thrashing, bug busting, discussions #117
  • @jordens visits JQI near the end of this interval
  • testing depends on M-Labs' "major steps for something interesting"; available between 2/1 and 2/15
• 2 weeks schematic update, layout fixes

if v0.2

The need for a second prototype round will be decided for each PCB. From date order is placed with board house...

• 3 weeks for printing, stuffing
• 1 week for WUT PCB checks (now they're rehersed)
• 1 week for international shipping
• 2 weeks for testing, thrashing, bug busting, discussions
• 1 weeks schematic update, layout fixes

v1.0

Design locked in... purchases are placed with board house (eg technosystem.pl)

• 4 weeks slack for procurement spool-up by prospective customers
• 3 weeks for printing, stuffing
• 1 week for WUT PCB checks (now routine)
• 1 week for international shipping

[jordens]

My best guess was 3-10 weeks after the tests at WUT have completed.

[jmizrahi]

Can I please get an update on where the timeline stands? Has the PCB order been placed? Are these PCBs being manufactured?

[gkasprow]

Hi The Sayma-AMC board routing is finished and the layout is being verified by Michal. Please have a look at it. After Michal runs the SI and PI analyses I will do the cosmetics, run net equalisation and generate production files. Frankly speaking I underestimated amount of work with Sayma board - it took much longer because at some point I had to reassign almost all FPGA connections and start routing from the beginning. Now it fits nicely on 12 layers. It took one week longer than I planned. Another problem was with Mentor license server at the University which was closed during Xmass period. The China will have its New Year and all factories are closed for 2 weeks so we will receive the boards at the beginning of February. German company, ILFA has 8+ week delivery time. In case of front panels the delivery of raw bezels is 4 weeks. They say that can make custom cutouts in 5-6 weeks. The Sayma-RTM routing is in progress. I estimate about 10 days to have it done. In case of Metlino I propose to make production run after we make Sayma running. 90% of the board is identical to Sayma and once we make Sayma AMC running, the Metlino will work as well. But it is up to you how we proceed. So far all critical components (FPGAs, connectors, SFP cables) arrived.

[jbqubit]

The Sayma-AMC board routing is finished

Excellent!

After Michal runs the SI and PI analyses I will do the cosmetics, run net equalisation and generate production files.

How long is that expected to take?

China will have its New Year and all factories are closed for 2 weeks so we will receive the boards at the beginning of February. German company, ILFA has 8+ week delivery time.

I thought technosystem.pl was slated to do the PCB printing and stuffing. Right? What boards are coming from China and ILFA?

The Sayma-RTM routing is in progress. I estimate about 10 days to have it done.

OK.

In case of Metlino I propose to make production run after we make Sayma running.

Let's decide on printing of Metlino once the routing, SI and PI analyses and net equalization is done.

So far all critical components (FPGAs, connectors, SFP cables) arrived.

That's great news. :)

[gkasprow]

@jbqubit Technosystem is assembly house. PCB printing is very complex process and only a few companies are able to cope with such technology. So we subcontract it to NCAB, ILFA, Brandner and many other companies. We should finish PCB verification in one week.

[jmizrahi]

@gkasprow I don't understand, every PCB fab house I know of can print 12 layers (or much more). Is there something driving the complexity beyond the the layer count? Can you tell me what you think the bottom line timeline is for the first prototype to be in-hand?

[gkasprow]

We use special RF material capable of 12 GHz operation. So only a few factories can do it. Anyway, the boards were designed for certain materials so we would have to keep the stuckup. So let's assume we get the boards at the beginning of February. We will need 3..4 weeks to make them running. There is a chance that we can have it quicker but let's be pesimistic. We will make 2 of them running, in the meantime we will assemble remaining boards. We will need to test them but one week should be fine. So realistic date is middle of March.

[jmizrahi]

OK, thanks for the timeline. What is the substrate? The 3-4 weeks to make them running includes the time to populate the components?

[gkasprow]

The substrate is ISOLA FR408HR The component assembly takes about 2-3 days and Technosystem does it. It requires P&P programme, SMT stensil, SMT assembly, THT selective wave soldering, automatic optical inspection. Then the boards are delivered to WUT where we verify all functionalities like power supply, mezzanines insertion, ripple measurement and optimisation, all clock circuits, SDRAM operation, GTH performance, mechanics, etc. It really takes a while and there are always some issues to solve.

[gkasprow]

Sayma RTM routing is 80% done. It is really tough, I have to do most things manually due to board packing. Sayma AMC was trivial comparing with RTM. But I will manage it.

[hartytp]

@gkasprow Any updates about progress on the Sayma RTM layout?

[gkasprow]

We are working hard on it.

Had some troubles with signal integrity of 10Gbit links and too high voltage drops on planes to the mezzanine connectors so had to rearrange routing.

However 95% of connections are done.

Hope to finish in 1 week.

[hartytp]

@gkasprow Great!

[jbqubit]

@sbourdeauducq created nice table in wiki for tracking prototype status. @gkasprow updated the wiki. Thanks guys. I'm deleting the now obsolete tabular I posted 14 days ago in this Issue to prevent confusion. Let's continue to use this Issue for related discussions.

[gkasprow]

well, I crated table with short summary for each board so others know which board is which. But in this table the summary disappeared

[gkasprow]

sorry, it is here https://github.com/m-labs/sinara/issues/155

[jbqubit]

@gkasprow What's the status of PCB_Sayma_AMC and PCB_Sayma_RTM?

[gkasprow]

All Power Integrity issues in Sayma AMC were detected and fixed. Now we are fixing SI issues. PCB manufacturer verified production files and sent list of things to fix. So we are very close. With Sayma RTM status is similar, I'm just fixing PI and manufacturing issues.

[jbqubit]

Great news! Thank you for the update.

[gkasprow]

For ones curious how PI issues tracking looks like, here is a screenshot of 4V distribution domain.

[gkasprow]

A set of boards just arrived at WUT

[jbqubit]

@gkasprow Are PCB_Sayma_AMC, PCB_Sayma_RTM and PCBmezzanine analog_allaki in proto production yet?

[hartytp]

ping @gkasprow any news about these PCBs (particularly Sayma RTM)?

[gkasprow]

Yes, they are in production. I didn't get confirmation date yet - PCB factory is preparing production masks. It took so long because we had endless troubles with Xilinx vivado ibis model for GTH and DDR3. I tried with 3 versions of vivado and each generated different ibis file. So different that with one model I got nice results while with another they were not acceptable. Old Xilinx ISE didn't cause such troubles. Finally I had to analyze ibis file (8MB of text) and learn how to modify it. I figured out for example that:

• sometimes, in completely random way the ibis file contains information about simulation mode- sometimes probes are placed at the die, sometimes at the pins which makes really big difference for pins with ODT.
• sometimes ibis file has missing lines with diff signal definitions. One has to add them manually, otherwise Hyperlynx generates errors or even crashes.
• sometimes differential lines are not defined so simulation tool treats them as single ended. Now I have a short manual how to process ibis files with certain error types :) Frankly speaking, this project was simulated and tested to such extend like I never did before. Many critical bugs were found which otherwise would not be found immediately during deugging but would cause issues later, i.e. with higher loading of FPGA or capacitor value depreciation with time. I'm pretty sure that with this effort pays off and we will save a lot of time later.

[hartytp]

Great! Thanks again for all the hard work.

Let us know when you're ready for us to place the order for our hardware.

[hartytp]

Nothing left to do here, so closing.