sayma development roadmap for 2017

[jbqubit]

The Sayma gateware/software development for 2017 needs to be sorted. Here's a breakdown of what's in the ARL and Oxford procurement pipelines. If there are additions or modifications to Task Groups A or C, Britton needs to know by 10/10.

Review of Tasks for end of 2016

The full Sayma design specification as presently envisioned is here. Below is a synopsis of the tasks slated for end of 2016 which are needed to demonstrate basic Sayma functionality. Anticipated Contract Start Date (CSD) is middle of October. This work is fully defined and is funded by ARL.

AWG Demo Timeline: CSD + 3 months Goal: demonstrate 4-channel 2-tone 200 MHz system working on KC705 with AD9154-FMC

• Datapath clocking and datapath pipelining/parallelization design, maximizing datarate, mini- mizing resource usage
• RTIO spline interpolators (frequency, phase, amplitude, offset) for parallelized DDS core
• RTIO spline data kernel/runtime support
• RTIO spline data handling (knot generation, indexing, scaling, embedding at compile time)
• Regular speed (fDATA/4 or fDATA/8) a,f,p-interpolating DDS cores (enabling two-tone out- put)
• Support for 4 channels at 300 MHz data rate (using 2nd Nyquist zone 150-300 MHz)

Synchronized AWG demo Timeline: CSD + 3 months; depends on DRTIO availability Goal: physicist-usable 200 MHz RF system using pair of AD9154-FMC (8 channels total)

• Best effort synchronization among DACs on FMC cards
• Latency matching of all RTIO channels

Ultrascale port, basic board support for Sayma and Metlino Timeline: Prototype board availability date + 1 month Goal: demonstration of Sayma-Sayma synchronization in uTCA chassis with Metlino as Core

• Device using DRTIO
• OpenOCD support for Kintex Ultrascale (JTAG interface support, bitstream loading, resetting, flash writing)
• Dual flash support
• JESD204 for Kintex Ultrascale (GTH)
• JESD204B synchronization and group-delay/latency alignment (subclass 1, gateware, clocking, synchronization sequence, synchronization monitoring) between different AD9154 chips and boards (as far as supported and exposed by the hardware)
• Port of DRTIO to Kintex Ultrascale
• Project management for Sayma and Metlino design
• Kintex Ultrascale DDR3
• Site visit to the College Park, MD (5 day duration) coordinated with arrival of prototype round 1 hardware (nominally 2nd week of December); includes travel, room, and board

  Task Group A

Tasks are needed for support of many-qubit applications. ARL is funding these items.

• 17A1 High-resolution (nanosecond-level) ARTIQ TTLs for Kintex Ultrascale type IOSERDES
• 17A2 Port single-tone non-interpolating RTIO parallelized DDS (fDATA) core to Kintex Ultrascale
• 17A3 Absolute and relative phase modes for all frequency and phase interpolators independently configurable through RTIO
• 17A4 f,p,a,u modulation by RTIO (eDRTIO) for all interpolators
• 17A5 DMA support (redirect RTIO events emitted in named DMA context to memory pool, then (re-)play by name)
• 17A6 Parallelizing CIC interpolator/AA filter before parallelized DDS core
• 17A7 Parallelized FIR filter after CIC, research and implement what’s possible given DSP resources
• 17A8 Coherent phase mode (implemented in kernel API and runtime) for frequency/phase updates of the three eDRTIO channels
• 17A9 Distributed DMA (for local DRAM on Sayma)
• 17A10 Continued project management for Sayma and Metlino testing and integration
• 17A11 Gate-able counter TTL input RTIO channel

  Task Group B

Full implementation of DRTIO is needed for communication with Sayma hardware both in uTCA chassis and over optical fiber. Oxford is funding these items.

• 17B1 Implement DRTIO: extend the demo implementation (https://github.com/m-labs/drtio_transceiver_test) into a complete solution, including output event injection / input event monitoring. The plan is for this functionality to be demonstrated on the Metlino / Sayma hardware.
• 17B2 Implement pulse-sequence DMA from the master system.

  Task Group C

Develop debug tools, support external modulation and increase Sayma dynamic range (in time domain). ARL is funding these items.

• 17C1 Time stretcher for interpolators to extend dynamic range beyond spline knot durations of 2**16 cycles
• 17C2 Saturating summing junctions
• 17C3 f,p,a,u modulation by external data stream (ePID) for all interpolators
• 17C4 Summing junction clipping detectors and their remote readout
• 17C5 Configurable, saturating output limiters
• 17C6 Monitoring support for all spline interpolators and total DAC output
• 17C7 Injection/override support for all spline interpolators
• 17C7 Distributed hardware logic analyzer support for all interpolators and DAC output

  Task Group D

Task Group D contains items not yet precisely specified and need hashing out as stand-alone github Issues. A subset of these tasks could be accomplished in 2017. Should there be other things on this list? Scope of some of these extends beyond Sayma.

• Hardware development supporting time-to-digital conversion (TDC) with 10 ps resolution. Focus is extending ARTIQ support to solid state qubits.
• Gateware and software development supporting 17D2. Aim to support in-loop feedback on timescales of << 100 ns.
• DAC output of sampled waveforms
  • for discussion see #6
  • suggested implementation: RTIO output channel that takes 8 samples per RTIO clock cycle (8 ns) and adds them onto the DAC samples just like the DC spline is added to the oscillators. Use DDR memory on Sayma_motherboard to maximize the sustained data rate.

    related to ADC

• JESD204B support for AD9656
• ADC sampling at full data rate #82
• ePID: drawing from ideas in D. Leibrandt http://arxiv.org/abs/1508.06319. See https://github.com/m-labs/sayma/issues/24.
• floating point support for soft core uP
• extending ARTIQ documentation: tutorial on modifying/extending ARTIO using DRTIO

[jordens]

@jbqubit Could you triage this issue (labels, milestones, somebody assigned, state what you would like to see done right now right here)? Aren't large parts of this redundant because already written down in #1 #3 #2 #6?

[jordens]

And obviously feel free to reassign.

[jbqubit]

I'm working on writing up Task Groups A and C. I'll revisit Task Group D in coming weeks.

[jordens]

Don't use the issue tracker for note-taking, planning, and brainstorming. Unless you have something that can actually be answered/done/resolved/fixed, this is not the right place.