3U DAC (Zotino) tests & rev 1 errata

[gkasprow]

Issues:

• [x] Use two output resistors in series/parallel to improve power handling (200mW short-circuit)
• [x] reverse C143, C145, C147, C84
• [x] mirrored SOT23 diode footprint due to Altium bug - part of component is on top layer, pads are on bottom layer.
• [ ] add Shottky diodes at the LDO outputs
• [ ] 3mm higher EMC shield on PSU
• [x] reverse IDC connector on BNC to IDC board
• [ ] Zero-index all channels
• [x] swap BNC connector GND terminals
• [ ] either add ~2mm plastic washers on BNC barrel behind front panel or move BNC connectors 2mm towards FP. This is to enable fixing the BNC connectors to the panel using the screws.
• [x] Please remove the annotation "This module connects to Kasli ..." and replace it with something like "EEM connector: IO are LVDS, I2C is 3V3 LVCMOS, P3V3_MP up to 20mA, P12V up to 1A."
• [ ] run PI and thermal simulations
• [ ] Can we run the digital interface from 2V5?
• Temperature controller issues:
  • [x] Decrease the thermal resistance between the thermal island and the main PCB/increase the thermal mass of the island by at least 1 order of magnitude -- without active stabilization, the DAC should only be 1-2C hotter than the main PCB. This should also improve the electrical ground connection between the main PCB and the thermal island.
  • [x] Remove current temperature controller and DAC over temperature shutdown circuitry.
  • [x] Add mounting holes/pads for peltier + heat sink controller by external circuit.
  • [x] Leave temperature probe on the thermal island, bring it out to an external connector, which should also provide +12V power, ground and I2C (maybe use I2C-controlled GPIO instead? This way we can do bit-banged SPI if we need to).
  • [ ] Assuming the peltier + heatsink mount on the top side of the PCB, do we want to add a stick-on insulation on the bottom side to screen the DAC from external air currents?
• [x] Silk + schematic + panel should be "v1.x" not "rev1.x"
• [x] Only have one set of +-12V regulators, not two!
• [x] Reduce SMPs outputs slightly, since we're only using +-12 regulators

Tests that can be done without an Artiq driver:

• [ ] Measure step response. This means measuring the 90%-10% rise time for a full-scale signal. If easily possible, also measure the 1% settling time.
• [ ] Measure noise PSD (0.1Hz to 10MHz) with full scale and mid scale output signal
• [ ] Glitches on LDAC, major carry, etc (trigger off the SPI)
• [ ] Confirm that temperature controller works. Measure temperature stability of DAC in lab conditions
• [ ] Measure drifts with temperature controller running. Set one channel to Vmax/0V, and look at drift over ~24 hours to confirm gain and offset drifts. Measure board temp co (e.g. use hot air gun to heat the board up while measuring output drifts).
• [ ] susceptibility to external EMI sources (i.e. neighbouring boards). I will test it with EMC equipment.

Tests that need an Artiq driver:

• [ ] Measure cross-talk (full-scale square wave at ~50kHz on one channel, another channel at 0V)
• [ ] Measure spurs due to SMPSs, digital-cross talk, pickup etc. Have one channel updating as fast as possible and measure noise on another channel
• [ ] Check for thermal issues (drifts) when outputs are slewing at max rate (e.g. testing for issues due to self-heating in the OpAmps). What’s the best way to test this?
• [ ] Measure harmonics with a full-scale sinusoid output at 50kHz.

Configuration for measurements is: DAC->3m SCSI cable->HD68 to IDC->IDC to BNC->scope/DVM/noise analyser. CMCs and a LPF on the IDC-BNC board as previously discussed. LPF chosen to avoid degrading the DAC noise or bandwidth too much.

[cjbe]

@gkasprow I check the DAC supplies in the overheated condition, both +12V and -12V are nominal.

[hartytp]

So, AFAICT, the absolute max operating temperature of the DAC is +85C, but the overtempeature cutout only trips at 120C...

[gkasprow]

so it seems that my DACs died in more spectacular way...

[cjbe]

@hartytp @gkasprow I have measured the noise of the Zotino with the filter input grounded, and the DAC removed (to not overload the SMPS). The noise curve is below (previous DAC at 0V data for reference): There still seems to be significant noise at ~100 kHz, even without the dying DAC heavily loading the SMPS

[jordens]

The low frequency stuff is mysterious. Shouldn't that SMPS be at ~1 MHz >> 50 kHz?

[hartytp]

Thanks for doing that Chris!

There's obviously something severely broken with this board. IMO there is no point debugging this further, given how much abuse these boards have been through. Better to move onto producing the v1.1 design asap.

[gkasprow]

@cjbe could you short the output CMC and repeat the measurement? It can pickup some external noise...

[cjbe]

@gkasprow I assume you mean short both coils of the CMC in order to effectively remove it? I am testing this with your 'ribbon to BNC' test boards, so there is both a CMC on the Zotino, and a CMC on the test board. I assume I should short both?

[gkasprow]

Yes.

[hartytp]

@gkasprow The broad-band noise also looks orders of magnitude higher than it should be, so I don't think this is the chokes (we always blame those poor things and they've never been the problem yet!)

Can we defer further tests until we've got the v1.1 boards ready, please?

[cjbe]

@gkasprow I shorted out the CMC's on a grounded channel - this did not significantly change the ~100 kHz noise, but increased the 50 Hz and harmonics pickup by >50 dB (so the CMC's are doing a good job!)

[hartytp]

Looks like (at least part of the problem) is the power supply lines.

If you want to try to track this down further, you could try replacing the SMPS with a bench PSU and see what happens to the noise. Also, that would let you check the current draw on the +-13V lines and check that they match the power budget...

[gkasprow]

I'd suggest one crazy thing - measurement without the power supply. @cjbe What tools are you using to measure the noise density? I'd like to recreate it in my lab.

[gkasprow]

@hartytp I updated schematics of Zotino and initial components placement

[cjbe]

@gkasprow I am using an R&S UPV Audio Analyzer. I will do some more sanity checks tomorrow to trying and narrow down the source of the noise.

[gkasprow]

I have access to Agilent SSA, in dedicated faraday cage room. I will check tomorrow what is the lowest frequency it can measure.

[hartytp]

Closing this as we're done with tests for Zotino v1.0. v1.1 discussion at #446