AD9910 PLL divider

[jordens]

Could someone with a AD9910 eval board check that a PLL divider of 10 works? The datasheet mentions 12 as the minimum and the PLL loopfilter spreadsheet only does 12. Is the REFCLK divide-by-2 in front of the PLL or not? There are conflicting statements on the internet. If the divider is in front of the PLL, a PLL divider of 20 would be the one.

http://www.analog.com/media/en/technical-documentation/evaluation-documentation/PLL_Loop_Filter_Tool.xls

https://ez.analog.com/thread/71428

[jordens]

I see only 2-5dB degradation of the AD9910 noise at 10kHz and 1MHz comparing the 156 MHz numbers with the 201 MHz.

[hartytp]

I see only 2-5dB degradation of the AD9910 noise at 10kHz and 1MHz comparing the 156 MHz numbers with the 201 MHz.

Maybe I'm doing a bad job reading plots on a small screen.

Either way, I don't think we care about it.

[gkasprow]

@hartytp we can connect it to free CPLD pin. Then in the code we can generate 3 output states.

[hartytp]

@hartytp we can connect it to free CPLD pin. Then in the code we can generate 3 output states.

ACK. But, a DIP switch is probably easier for the user. Software control is not required for this pin IMO, so it's better just to use a switch.

[hartytp]

@gkasprow Sure, but let's connect it to the dip switch as well. That way, using the switch it can be set to either div=1 or div=2 (which are the important cases).

[gkasprow]

@hartytp We will do it via CPLD :)