Urukul v1.0 errata

[gkasprow]

• [x] Subsignals like IOA_n should be renamed to something like EEM0_n or IO0_n since we renamed the EEMs from EEMA/EEMB to EEM0/EEM1.
• [x] Use a currently unused CPLD pin for DDS select: pulled high by a 0R resistor if AD9910 populated, pulled low if AD9912 populated. (In the current version, we have to use the dip switch, which is less convenient for the users).
• [x] R52 and R47 are still wrongly DNP in the AD9912 variant
• [x] place ARTIQ/Sinara logos on the PCB
• [x] Silk + schematic + panel should be "v1.x" not "rev1.x"
• [x] connect BIAS of IC7, IC11 to Vcc >Vout+1.3V, in our case 5V. IC18 BIAS is connected OK.
• [x] decouple BIAS of IC7, IC11 with 1µF
• [x] make sure that the PGOOD LED does not light up when there is just 3V3_MP but no 12V
• [x] Fix power budget for Si53312 and Si53304
• [x] modify R118/R119 and R23/R80 - add 820R in parallel or replace
• [x] RF amplifier has wrong part number which indicates straight leads while we need bended leads.
• [x] add insulating washers to the BOM
• [x] the SMA connectors have wrong mechanical models - missing ring. In fact, additional metal washer is needed to support internal plastic insulating washer.
• [x] fix the test pad names, net names, and silk screen labels: on the CPLD page net TP0 is connected to TP5 etc. Also TP5-TP8 exist both on the CPLD page and on the power supply page. They are also labeled that way on the silk screen. I.e. there ate two different TP5 on the board!
• [x] separate away clock input LVDS lines
• [x] add current limiting resistor for attenuator output
• [x] Add MOSFET switch to the oscillator
• [x] Annotation about EEM connectors ("EEM connector, all signals are LVDS ...") should be changed to match the same annotation we've added to all other boards
• [x] Annotation about thermal shutdown states that the power consumption is >12W. That's not true. Maybe just leave out the statement about exactly how much power is dissipated.
• [x] Please can you add an annotation on the schematic noting that if the user populates the capacitors to use the MMCX clock input they should depopulate the inductor supplying power to the oscillator to prevent leakage.
• [x] Add MLVDS receiver type control from CPLD

[jordens]

@gkasprow A lot of the pins of the LVDS-to-CMOS converters did not reflow correctly. Do you need photos or do you see that as well?

[gkasprow]

sure, post it. Technosystem gives warranty for the assembly so it's their deal.

[gkasprow]

@jordens I can see them on my boards too...

[jordens]

We don't have the time to send the boards back for them to fix it. So we'll fix it ourselves. But I'll post the photos nonetheless.

[gkasprow]

OK. I will send them the boards I'm not using at the moment

[jordens]

The photos are here: https://share.quartiq.de/s/KGZOJ60rIPNyvKU

https://ibb.co/ht3A7w https://ibb.co/cTcEZb https://ibb.co/mSR8ub https://ibb.co/nkQJub https://ibb.co/b5q7nw https://ibb.co/kHvZZb

[jordens]

News to me, from TI SLUA271: "IPC-A610D does not require a side fillet, since the side terminations are not plated. While it may appear the wetting is reduced on the side of the component, the solder joint underneath is not affected." I.e. we need to ensure proper wetting by x-ray/electrical.

[jordens]

@gkasprow Regarding the patching of BIAS of IC7, IC11: I am a bit worried about the lack of decoupling now on that pin. Could you add 2x1µF on that wire somewhere close to chips when patching the other boards?

[gkasprow]

I added. But this is only FET biasing, so should not cause any issues. It consumes very little power.

[hartytp]

@jordens Out of curiosity, what's the objection here? AFAICT on the current schematic, there is already a 1uF ceramic on the BIAS pin of each regulator (C165 and C77). That's what's recommended by the data sheet. So, AFAICT, we don't need more components added to the schematic, right?

Is the objection that the placement of these capacitors isn't close enough to the BIAS pins on the ICs?

[gkasprow]

Nope. But I cannot cut the trace and leave the capacitor connected. So had to add another one, close to the BIAS pin. The distance of the capacitor is not critical since almost no current is flowing.

[jordens]

@gkasprow Ack. There is little current. But iirc the ldo reference is running from and thus it needs to be low noise.

[a-shafir]

I have not reviewed the board in details but i already noticed some improvements that can be done:

1. add source serial termination resistors close to CPLD on SCLK or better on all the signals. This CPLD >has no internal termination in IO and we need to keep FAST slew rate for the performance. So there can >be ringing that can reduce the usable SPI clocks as well as the analog noise since the control traces are >long and all around the PCB. Note: the SPI clocks can go up to 66MHz by the concept and it must be >terminated.

How can you terminate multipoint clock and data connection? The clock is distributed to 4 SPI chips. To do it correctly, on would need to use 4 CPLD pins and 4 series resistors. The same for other signals. Only DDS_RESET line is source-terminated (need to be well matched) but this is not optimal because we won't have good matching anyway due to CPLD output resistance. So existing solution is kind of compromise between what we could do and what we can reasonably do. Note that there is already AC termination on SPI data and clock (R40, R41, C87, C26). This reduces ringing, but as I said, you cannot really terminate it properly.

2. add some protection to the SMA connectors, especially the clock input. Currently it can be easilly burn both by ESD and an incorrect clock source.

Not that easy, somebody would have to touch the hot pin. Any design can be broken if you apply 230V AC :) The same applies to the outputs - somebody can connect too strong signal... Take into account that TVS is non-linear part and it may cause signal distortion.

3. replace 100nF on the clock patchs (C196 etc, there are many). That 100nF are not really good parts for >tens MHZ signals. 10nF RF class parts shall be more appropriate.

we are talking about 100MHz max. At this frequency the capacitor we use has 0.2R of impedance, so we can ignore it.

4. Check all non-RF the traces on the RF side of the board (ATT_CLK, ATT_S_OUTs etc, basically all of >them). I think need to do more debouncing and source termination resistors everywhere since it is a >obvious source of interference with the analog circuits.

These are CMOS lines. If you terminate them, you will introduce additional current and increase amount of interferences. Essentially, additionally to the capacitive coupling you will get inductive coupling. I wouldn't put resistors "everywhere", but only in the places that really make sense. One can consider series termination on the clock line or AC termination at the load. But take into account that series termination works only if load capacitance is very low. In case of standard CMOS input this is not really the case. Anyway, these registers have limited max clock rate to 30MHz

5. For any "potentially user configurable" parts use bigger package than 0402 and label them. That's correct. We discussed several times and for most of the users 0402 is not a prolem. Take into account that the bigger the component is, the higher parasitic capacitance is and worse impedance matching. So it is always a compromise.

6. Check the signal paths of CKIN1_P/N, CKIN0_P/N. Curretnly it is not well balanced and if there are 2 active clock sources (INT and SMA) it can easily interfere. Also there are some potentially noise power lines along the clocks and it certainly can be shifted closer to the board edge and shielded/separated better.

They are already shifted to the edge. You cannot place the clock lines at the very edge of the PCB because it causes EM field distortion and you won't be able to maintain correct matching. It also increases radiated EMI. It is very unlikely that somebody would use both clock sources. But OK, I will separate them because they are too close. Good catch.

[a-shafir]

@gkasprow

1. About the termination. It needs serial termination at source. Like 22-33R serial next to the source. Ideally it can be optimized for the traces/stack used in the project. The optimal value can be tested or simulated. 33R shall be fine.

Note: There ARE in fact separate control lines for each DDS. Check DDS_SCKI0 and others on the Altium. It can be nearly ideally terminated both at source and at the end of each trace, there are nearly no multi-point. There 9910 and 9912 are near comparing to the length of the trace. Moreover a jumper resistor can be added between 9910 and 9912 and removed in 9912 case so it will be nearly ideal signal line.

4. ATT_CLK can be fixed to be non-forked by moving the CPLD trace up. Also can be serial termination on CPLD side or even parallel next to IC3D. ATT_S_IN is single tap straight. ATT_S_OUT and the junctions between the ATTs can be easily terminated at source, there is plenty of space.

5. There is no protection at all. It is even terminated on the clock chip. I am sure it can be added. Simplest will be 2 diodes protection to GND and to a locally filtered 3.3V. Ideally need a protection and a buffer (singe ended to differential) next to the sources connectors. I think the buffers noise will not be a problem since the DDS PLL filter will not pass it. But interference from the power etc is low freq and more dangerous imho.

6. It shall work. I just saying that 100nF does not looks like RF signal path component coz of parasitic etc.

7. Of course need a ground shielding traces (with multiply vias to the ground plane along the pcb edge as well between the clocks pairs and other signal. It can be done nicely and symmetrically - there is enough space. No emi concern because it differential (at least shall be balanced differential if proper buffers used, see "2".

IMPORTANT: DDS and ADC/DAC boards have analog specs. So it will be "not perfect" any way, will be some noises and other specs degradation. And we have constrains of the size etc. But I am sure some important improvements can be done with minimal efforts and cost comparing to the existing design and BOM.

[cjbe]

@gkasprow on the Urukul I have it is not possible to fully mate to the front panel SMA connectors as only ~5mm of the barrel is accessible when the connector fixing hardware (plastic washer, spring washer, nut) is attached.

[a-shafir]

@cjbe @gkasprow yes, the SMA connector needs some improvement:

• need longer/extended thread connectors. There are some.
• need a thick (or few thin) washer between the connector and 1st plastic washer to be able to tie properly the nut.
• need to move the connectors and the LEDs bit closer to the panel, currently there is about 0.5-1mm "wasted"
• in case of the "short" connectors will stay the same the spring washer can be removed. It shall be fine since a flexible plastic washers used. Also some Locktite can be used for locking the nut.

Having all this done shall make it mechanically better and also will allow full mating.

NOTE: basically all the SMA boards can use share the optimal (optimized) SMA (and BNC)/LED/isolator/washers etc stack. So will not need to handle this issue anymore.

[gkasprow]

@a-shafir You are right. But in DDS board SPI data and CLK are already load-terminated, so there is no issue. I'm sceptical about source-termination of a line that goes to multiple capacitive loads. 30R is not treated as source termination but rather as a kind of RC filter to make edge transitions smoother and to get rid of oscillations. Source termination need to be matched to the Z of the line and the end of line must be opened at the end. So let's not talk about termination but data edge smoothing :) Did you actually look with a scope at these lines? What is the CPLD output resistance? Maybe it is already an order of 30Ohm so there is no issue at all.

In case of diff lines it's hard to make shielding for lines on top or bottom layer :)

[gkasprow]

@cjbe I tried prior shipment and it looked fine. Maybe my SMA connector was slightly shorter. Anyway, the mechanical 3D model is different than actually mounted connector. I already added this to the list of fixes to do.

[gkasprow]

@a-shafir concerning these LEDs, are you talking about Urukul? I aligned them to make sure they touch the panel. On previous boards like ADC and DAC there was such issue.

[a-shafir]

@gkasprow you right there is a load termination on the major DDS lines. I am not sure about 200R (as well about 50R on the RF). Have you simulated it?

It is still no termination on ATT lines. And the ATT is further on the signal patch and potentially is dealing with the attenuated signals so the SNR is more crytical.

A scope is barely useful for testing it. I think the best is compare the output noise when SPI is not active with the noise when SPI busy on DDS or ATT.

By shielding i mean Faraday-caging. And also symmetrically placed. Basically to have the perfect signal line (quite long in case of clks) it shall be all-differential and placed properly with the signals/grounds around. I don't think that it make sense to move it to internal layers in this case. I have more concern about the single-ended to differential conversion in this case. Yes, it is not good idea to use both clock connectors simultaneously. But it needs to be warned in the board manual.

Another problem that if we use the internal 100MHz oscialltor it can't be disable so in it can be a serious interference issue with 100MHz-like input clock in this case. Btw, the OSC can be disabled via a power switch FET.

Yes, there are some strange gaps on Urukul we have here. Can you see it on your board?

I think for the proper assembly need to tie the SMA nuts first. Also add washers or replace the SMA connectors to have the plastic washers properly sit on the connector body. And only than tie the PCB mounting screw.

For the best result i suggest verify the SMA and LEDs connectors holes to assure it aligned strictly and the same along the line. And for the mounting holes i suggest bigger size or oval shape so it will allow precise and simple assembling (with some instructions for the factory).

[a-shafir]

[hartytp]

@jordens Had a closer look at the bias capacitor issue you raised:

• Datasheet p4 note (3) "If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 µF." AFAICT, this only applies to IC18 (IC11 and IC7 are biased from 5V and supplied from 3V3). It might be worth swapping the bias capacitor to 4u7 here. (In practice, I suspect that there is so much capacitance on the 3V3 rail already that this is not necessary, but probably good practice).
• For IC11 and IC7 I don't see any reason to add more capacitors. The datasheet specifies a minimum capacitance for the BIAS as 100nF, with 1uF the preferred value. The reference and many of the specifications use a 1uF capacitor. However, we could swap to 4u7 if you'd rather...

[jordens]

@hartytp Right now there is a long wire going across the board to BIAS of IC7 and IC11. And on the first board that I received there were no caps on there. That wire definitely needs decoupling.

[jordens]

@gkasprow Also, the PGOOD LED lights up as soon as there is 3.3V supplied over the VHDCI cable. It should only light up once all power supplies are good. I added a note to the top post.

[hartytp]

@hartytp Right now there is a long wire going across the board to BIAS of IC7 and IC11. And on the first board that I received there were no caps on there. That wire definitely needs decoupling.

Sorry, I mis-understood, I'm with you now.

If I understand correctly, there are already capacitors on these bias pins in the design (C77 and C165). However, because the bias was incorrect, the traces had to be cut, so those capacitors were disconnected. So, this issue should be fixed once the bias is fixed, which is already on the to do list.

And, you're right, we should definitely add these capacitors on all v1.0 hardware that has been produced. Good catch!

[hartytp]

@cjbe Are you okay to add those capacitors onto the boards we have (we should do this before building them into any experiments)?

[jordens]

Greg is doing that AFAICT when patching.

[gkasprow]

Some of the boards were already shipped when we realised that the caps should be there. So some of them has them and some of them don't.

[hartytp]

Good to know. Will look out for that on our boards.

[gkasprow]

Anyway, the bias pin is supplied from 5V LDO so the only issue would be with externally induced noise.

[gkasprow]

@jordens I'm preparing rev 1.1 and to keep firmware compatibility I moved IFC_SEL3 to pin 112 and connected 0R resistor to VCC to pin 111 were IFC_SEL3 was initially connected.

[jordens]

Ack

[gkasprow]

@jordens I implemented all issues in Urukul. Please have a look.

[hartytp]

One thing still outstanding from the v1.0: I still haven't checked the phase noise performance or optimised the loop filter yet. Not sure if you want to wait for that before manufacturing any more boards?

[jordens]

The phase noise performance was measured.

[jordens]

@hartytp The v1.0 AD9910 noise is in the testing issue. That's OK for me right now. I don't want to delay manufacture just because of loop filter tweaking. If you need to quickly do loop filter tweaking, until when would that be? The AD9912 uses the datasheet values and at least locks fine. I don't have measurements yet for it's PM spectrum but the datasheet is a good indication. That's sufficient for me.

[jordens]

@gkasprow [Not a manufacturing issue] There are still two instances of TP[12345] on the schematics. That's at least confusing. Otherwise ACK to the other changes.

[gkasprow]

OH, you meant signal name not matching the designator :)

[jordens]

Yes. You can call it that. It's a minor thing.

[gkasprow]

OK, fixed.