Closed gkasprow closed 6 years ago
Define "start".
HMC830 wasn't locking
No, it's before even Misoc logo appears in terminal.
I would suspect there is some Sayma-bug around the flash that prevents the FPGA from reading it and loading its bitstream fast. Check the DONE pin to find out. Note that if you tweaked the bitstream instead of building it straight from artiq/migen/misoc, you could have changed the flash readout settings too.
It starts itself after a minute. Then it works fine. I will have a look at done pin
czw., 9 sie 2018, 17:58 użytkownik Sébastien Bourdeauducq < notifications@github.com> napisał:
I would suspect there is some Sayma-bug around the flash that prevents the FPGA from reading it and loading its bitstream fast. Check the DONE pin to find out. Note that if you tweaked the bitstream instead of building it straight from artiq/migen/misoc, you could have changed the flash readout settings too.
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Btw,there is LED on the panel tied to the done pin
czw., 9 sie 2018, 18:14 użytkownik Grzegorz Kasprowicz kasprowg@gmail.com napisał:
It starts itself after a minute. Then it works fine. I will have a look at done pin
czw., 9 sie 2018, 17:58 użytkownik Sébastien Bourdeauducq < notifications@github.com> napisał:
I would suspect there is some Sayma-bug around the flash that prevents the FPGA from reading it and loading its bitstream fast. Check the DONE pin to find out. Note that if you tweaked the bitstream instead of building it straight from artiq/migen/misoc, you could have changed the flash readout settings too.
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Are you saying there is a delay between DONE and the bootloader output? There are only idelay calibrations and pll locks going on on that time. If they take long something is really fishy.
No, I just said that there is LED tied to DON pin, but it means I have to check how much time it takes to configure.
It is DONE pin that goes high after such long time...
I never saw that on that board.
It looks like the configuration takes longer than usual. maybe FPGA reads entire memory instead of part of it? Eventually it manages to configure both FPGAs correctly. On some boards I played with Vivado tools and programmed the FLASH memory, maybe Vivado left there something that now makes booting longer?
I don't see what could be left. If artiq has been flashed recently the relevant parts of the flash have been overwritten. But if you flash a artiq .bit using vivado then the loading options can be changed on the fly and can be slow.
As I said, @gkasprow I've never seen this issue on that board using artiq_flash
so I don't think there is a real hardware/artiq issue here.
No, I flashed it with artiq_flash recently, but before was playing with vivado tools. So there is some issue which would be nice to explain before we produce v2.
Note that if you tweaked the bitstream instead of building it straight from artiq/migen/misoc, you could have changed the flash readout settings too.
It was probably this issue. I changed eth rx clock phase with tcl script. When I built bitstreams again, this time changing value in misoc, artiq starts immediately.
@sbourdeauducq I noticed that on the board I got from @hartytp today the ARTIQ starts after several tens of seconds. Another board in my lab behaves in the same way. Other boards start immediately. What enable the bootloader to start? What reset signal do you use?