Closed hartytp closed 5 years ago
NB need to be careful with the logic level conversion here since the optimal common-mode voltage for the SYSREF inputs is 600mV. So, need a resistor network to match that to the LVPECL/CML/whatever driver.
NB in my tests, I'm using AC-coupled LVPECL since it would be very tough to add such a network to Sayma (too fine pitch everywhere, no convenient access to ground, etc).
It's easier to remove terminating resistors and switch to LVDS mode. At the moment the termination resistors are soldered directly to the DAC pins. AFAIR I did it not only for clock but also for sysref inputs.
@gkasprow @hartytp What is the conclusion here? In schematics SYSREF is AC coupled, has 100R differential termination and 200R to ground at source.
Source: DAC:
Closing in favour of https://github.com/sinara-hw/Sayma_RTM/issues/13
200R is pulldown for open emitter outputs. 100R is differential termination. Such a solution consumes far less power than Thevenin termination.
Sysref should be DC coupled and 50Ohm terminated at the DAC. Currently, it's AC coupled and untermianted (AFAICT, the DAC sysref inputs are high-Z).