Closed jordens closed 7 years ago
I did some estimation. We can easily fit four 32x100mm DAC/ADC mezzanines on RTM. We can even make them longer. On each of them we will fit four Wurth 30x30mm shields placed on both sides. In case of RF connectors I consider using: 2 high performance SMA, edge mount for DAC output 2 lower performance, right angled for ADC input. 8 SMP connectors for ADC/DAC. THT version with SMD central pad would give best mechanical properties. The distance between mezzanine and RTM is 9mm which is minimal value for SMP+bullet. For digital IO and control I'd like to use Samtec hermaphroditic, 40 pins connectors: LSS-120-01-L-DV-A and LSS-120-02-L-DV-A which combined give exactly 9mm. I use them in other projects and they work well with frequent mating. Mechanical mounting would be ensured by 4 x 2.6mm holes, 4 threaded spacers and 8 M2.5 screws. There is still place on front panel for SMA clock input I placed typical bulky SMA connectors to check the clearance between them. It is not that bad. Then are accessible with the wrench when the RTM is outside of the crate. Attached are PDF3D files with mezzanine and RTM. mezzanine.pdf RTM_DAC.pdf We will leave the space below mezzanines to enable the air flow. Some cut-outs in RTM may be necessary as well.
The clock module dimension is 43x80mm We can make it slightly longer when necessary here is the RTM with clock module RTM_DAC_clk.pdf
Thanks! Impressive.
I cannot open any of those PDFs, either with mupdf or Evince.
$ mupdf mezzanine.pdf
error: expected trailer marker
error: cannot parse trailer
error: cannot read xref (ofs=617742)
error: cannot read xref at offset 617742
@sbourdeauducq Yes. As far as I know PDF3D can be opened only with proprietary Adobe Reader for Linux.
Adobe Reader freezes when trying to open those documents.
Is there another format we can use for this?
we can use step
On 1 October 2016 at 18:10, Sébastien Bourdeauducq <notifications@github.com
wrote:
Is there another format we can use for this?
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To view step files I use free Design Spark Mechanic.
FreeCAD is very bad but it should suffice to view STEP files.
Due to 10MB limit I had to zip them CLK module.zip mezzanine2.zip RTM_DAC_clk.zip
In case it pdf 3D files you have to use recent Adobe Acrobat Reder
Is this still with the SMA firmly screwed into the front panel? How would the mezzanines mounted in >that case?
the mezzanines are mounted to the RTM board using 4 M1.5 screws
Did we want no common LO clock (for whatever upconversion needs there may be) to the >mezzanines? I'll add another SMP connector I assume that there is still space for the dacs, adcs, power supplies, and clock fanout? sure, some of them can be plalced below the mezzanines
Is this still with the SMA firmly screwed into the front panel?
There are versions with long thread both right angle and straddle mounted. But their performance need to be verified since they are low cost. http://www.amphenolrf.com/132289.html http://www.rfstreet.com/ch_contentd.asp?id=2043 on the other side the assembly of the modules changed - they will be firmly attached to the rigid RTM board by 4 screws so it may be not necessary to screw them to the front panel
Thanks. The STEP files work fine with FreeCAD. FYI, the Acrobat Android app and the Chrome PDF viewer also choke on the PDF3Ds.
What is the idea behind having more SMPs than SMAs on the mezzanines? Since this also results in more SMPs than DAC/ADC channels on the RTM carrier, how will they be connected?
Did you enable the 3D view in AR?
It needs a while while opening the file
Greg
The signals of the ADCs and DACs are differential, that's why we need the SMPs doubled. The mezzanines inputs and outputs are single ended. The idea is to place baluns on the mezzanines because the way one feeds the ADC or couples to DAC depends on application.
Aren't SMP connectors designed for single-ended unbalanced signals?
Well, in this way you can say that traces on PCB are designed for single ended signals. If you make differential traces that are loosely coupled, you can treat them as single ended. When you make traces tightly coupled, then they interfere with each other and if you split them then their impedance will increase. The same applies to SMAs - on every devkit you can connect gigabit transceivers using single-ended connectors. To transfer signals using SMPs you have to make impedance conversion from tightly coupled diff line to loosely coupled diff line and then transfer via connectors. So to make 100Ohm diff line you can use 2 traces wit 50Ohm but separated far away or use two 70Ohm traces coupled in such way that trace field see each other. In first case you can transfer them wia SMP, SMA or whatever, in second case you have to transfer the line to the first case.
On 2 October 2016 at 17:08, Sébastien Bourdeauducq <notifications@github.com
wrote:
Aren't SMPs designed for single-ended unbalanced signals?
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on every devkit you can connect gigabit transceivers using single-ended connectors.
Yes, but I've been suspicious of this and wondering if it were just a cheap hack. Is it actually working well?
This works perfectly fine. Convince yourself using the method of image charges and symmetries.
It's very hard to find true differential signal connectors where the channel-to-channel crosstalk is anywhere near as low as if one uses two coaxial connectors (e.g. SMP) for a differential signal. Sending the ADC/DAC differential signals over pairs of SMP connectors is the best compromise we could come up with given crosstalk/space/price/bandwidth/mating limitations and requirements.
Impressive drawings!
Wurth 30x30mm shields placed on both sides
- Should these also cover the back side where the SMP penetrate?
- A single shield on each side would give more freedom for component placement.
- What's the maximum vertical height for components? Is this sufficient for bulky components like baluns, transformers?
Is this still the plan?
Several points:
The Wurth shields were only placed just to reserve place on PCB. There are smaller ones like these http://www.digikey.com/product-search/en/rf-if-and-rfid/rf-shields/3539677?k=&pkeyword=&pv1217=1&FV=fff40036%2Cfff802dd%2C13040001%2C13040009&mnonly=0&newproducts=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25
Again, the shields you quote are not tall enough inside, nor would they extend the full size of the board. I understand the Wurth shields are placeholders, but I think we will probably want something custom/multicavity that covers as much of the board as possible while separating the various channels from each other.
In this case we can use custom Harwin shields (EZ-shield) where they can be freely adjusted with 5mm step. You just install clips on the PCB and then manually form the cover. http://www.mouser.com/new/harwin/harwin-ez-emi-rfi-shield-cans/
OK. @dhslichter and @gkasprow if you feel that you have arrived at a workable solution, please close the issue. AFAICT the rest has weighed in. And @sbouhabib. I'll assign it to @dhslichter once he has accepted.
@gkasprow can you clarify on which SMA connectors you want to use on the front panel, and their layout? Let's try to put the whole spec into a single comment at the end of the thread before we close.
Here's my summary of current design choices for mezzanine interface (and geometry) for each of 4 analog boards. @jordens @gkasprow @sbourdeauducq @dhslichter please review. @weidazh please forward to Harty
geometry and mechanical
RF shield
PCB material/layers
connector choices
power/IO header routing
ADCs
@jordens Does github permit making an Issue comment as "sticky" so it rises to top? Seems like that's where the summary should lie.
During our last discussion we decided: +6V 1.5A. This minimizez LDO losses. We don't need -7 for RF stuff. +12V 200mA -12V 50mA no need for other power lines. I'd add local I2C line for module identification - the same mechanism as is on the FMCs. In this way we will quickly know which modules are installed in certain mezzanines. With all system enclosed in the rack it's good to know what is inserted in each RTM. To save pins, the I2C lines can be connected to the I2C muxes and later on to the Artix FPGA and in parallel to the IPMI link. To supply EEPROM and some digital stuff 3.3V is needed with low current capability. Now the connector looks like this;
Here is the final summary, based on comments from @gkasprow and @jbqubit in this thread. Items labeled ACTION: are not finalized yet; I will edit this comment with the correct information once they are finalized. @jordens @gkasprow @sbourdeauducq @jbqubit @weidazh please provide feedback.
I2C voltage is 3.3V. The calibration ADC is on the RTM board, controlled by Artix FPGA>
SMP part no is: MOLEX 85305-0232 for DAC signals Amphenol SMP-MSLD-PCT-10 for ADC signals With such scenario we will keep DAC signals on same layer and ADC signals on opposite layer. SMA part no is: Telegartner J01151A0451 for DAC signals. It is the only choice for desired performance. Telegartner J01151A0921 for ADC signals. This selection is forced by type of SMAs used for DACs. No other type of connector will fit.
There are still 4 unused pins on the power/IO header. Would it make sense to use these to make the ADC input lines into differential pairs? Thus there would be 8 pins total going to the slow ADC, which could be either used as 4 differential pairs or 8 single-ended lines with a chip like http://www.analog.com/en/products/analog-to-digital-converters/ad-converters/ad7173-8.html
I'd reserve them for future use. For sure we will find some application for them
On 11 October 2016 at 00:02, dhslichter notifications@github.com wrote:
There are still 4 unused pins on the power/IO header. Would it make sense to use these to make the ADC input lines into differential pairs? Thus there would be 8 pins total going to the slow ADC, which could be either used as 4 differential pairs or 8 single-ended lines with a chip like http://www.analog.com/en/products/analog-to-digital- converters/ad-converters/ad7173-8.html
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@gkasprow especially on the +12V and +6V rails, we need to make sure that the power line filter components are carefully chosen. 0201 package 1 nF capacitor will likely have very substantial DC bias dependence to capacitance (esp. if caps are only 16V rated, I would use larger margin for +12V rail), for example, and we should check choke impedance at 1.5A load for +6V rail.
Temperature monitoring can also be performed on mezzanines by using ADT7420, which contains conversion and I2C hardware, thus freeing slow ADC lines for e.g. monitoring of I/Q modulator drift or amplifier gain drift.
we can use 0402 NP0 instead
The chokes are rated for 3.5A BLM41PG181SN1L
On 11 October 2016 at 00:23, Grzegorz Kasprowicz < G.Kasprowicz@elka.pw.edu.pl> wrote:
we can use 0402 NP0 instead
I vote 0402 NP0 for the 1 nF, and X7R with higher voltage rating on the 10 uF if possible. Chokes look good.
thus freeing slow ADC lines for e.g. monitoring of I/Q modulator drift or amplifier gain drift.
We also have an ADC inside the XC7A15T.
@jbqubit rises to the top of what? What you perceive as important might not be what is currently relevant to others. If you are certain this particular issue is more important than the other "important" issues, give it the aproriate label. You have lots of options to view issues in the way you prefer.
@dhslichter looks good to me (apart from my usual concerns about layout density)
@sbourdeauducq I am less concerned about the number of available ADC channels, was more thinking about the number of ADC signal lines coming out of the mezzanine (set at 4 right now). For a typical IQ modulator setup, we might be monitoring voltages (via lowpass filters) at the I port, Q port, RF port, and after the output amp, thus would use all the ADC lines in the I/O header for those and not have any for temp monitoring; the I2C temp monitor helps with that.
@jordens ack.
@gkasprow where will the SMP connectors providing a 100 MHz clock to the mezzanines go?
Do you mean RF_LO signal? The idea is to provide RF clock for up/down converters on the mezzanines. So I want to place SMP connectors routed to the clock module which may in the future provide such signal In case of the EXT_100M_RF_IN, it is routed directly to the SMA on RTM front panel.
I am thinking of a reference clock (e.g. 100 MHz) that will allow one to place a VCO/PLL on the mezzanine for generation of an LO to be mixed with the I/Q signals from the DACs to give an upconverted waveform. We had discussed the option of this architecture in addition to having the LO generated off-card and sent to the mezzanines via front-panel SMA.
So yes, one would want to have an SMP pair routed to the clock module from the Sayma board, or else via an SMA cable from the clock mezzanine. I believe Tom Harty had some notions on this laid out.
Here is the final summary, based on comments in the thread below. This post will be sticky at the top, containing the most current specification. Items labeled ACTION: are not finalized yet; @dhslichter will edit this comment with the correct information as it is finalized.
Mezzanine geometry/stackup
Connectors
Power rails
Power/IO header routing