Here is the final summary, based on comments in the thread below. This post will be sticky at the top, containing the most current specification. Items labeled ACTION: are not finalized yet; @dhslichter will edit this comment with the correct information as it is finalized.
Mezzanine geometry/stackup
mezzanine board 32 x 100 mm, .047" nominal thickness, 4 layer boards
top and bottom layers to be Rogers 4350B, .020" thickness (cap construction for PCBs)
50 ohm CPWG on .020" Rogers 4350B is .035" trace with .011" gaps
need ground stitch vias every ~.050" or less along both sides of CPWG
mezzanines are mounted to RTM motherboard using 4x M1.5 screws
9 mm stand off between motherboard and mezzanine
RF shields on both sides, separate cavities for each DAC channel and ADC channel (4 total per mezzanine)
interior height under DAC side shield lids needs to be .170" minimum (allowing for fabrication tolerances) to accommodate baluns
interior height under ADC side shield lids .120" (3 mm).
Connectors
power/IO: Samtec hermaphroditic, 40-pins connectors: LSS-120-01-L-DV-A and LSS-120-02-L-DV-A
DAC side of board: 2 SMA (Telegartner J01151A0451)
ADC side of board: 2 SMA (Telegartner J01151A0921)
ACTION: use multi-coax assembly for front panel?
Power rails
+12VDC @ 200 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
+6VDC @ 1.5 A, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
-12VDC @ 50 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
-6VDC @ 150 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
no switching "spikes" on rails
pi filters on all power lines
0402 NP0 1 nF cap (16V min rating) parallel 0805 X7R 10 uF cap (16V min rating - Samsung CL21B106KOQNNN or equivalent DC bias performance -- degrades to 7.5 uF @ 3.3V, 5.5 uF @ 6V, 2.7 uF @ 12V) to ground, between mezzanine and choke
BLM41PG181SN1L choke
0805 X7R 10 uF cap to ground (16V min rating - Samsung CL21B106KOQNNN or equivalent DC bias performance), between choke and supply
desired supply voltages to be generated from these rails on mezzanine with dedicated LDOs
no switching supplies on mezzanines
+3.3VDC @ 1 A for digital-only devices on mezzanine. Should still be filtered on Sayma to minimize noise. max 10 mV p-p noise in 20 Hz-20 MHz bandwidth acceptable.
single shared ground for analog and digital, connected to all SMP shields and all ground pins of power/IO connector
Power/IO header routing
as shown in image below from @gkasprow with exceptions listed below
power line filters to pi filters as described above.
digital lines IO0-IO15 3.3V LVCMOS
I2C SDA/SCL (3.3V), pullup resistors to +3.3V installed on Sayma. I2C fed from I2C mux chips on Sayma card. Easy/compact level shifting on mezzanines (if needed) using discrete MOSFETs: http://www.nxp.com/documents/application_note/AN10441.pdf
digital IO are general purpose in hardware, but for SPI preferred pinout is:
SCLK = IO0
MOSI = IO1
MISO = IO2
CS = IO3
additional chip selects starting with IO4 and up
power rails as shown (7V rail is actually 6V)
4x connections to slow ADC (24-bit sigma-delta) for drift/temp/etc monitoring. ADC chip is mounted on See #11.
Here is the final summary, based on comments in the thread below. This post will be sticky at the top, containing the most current specification. Items labeled ACTION: are not finalized yet; @dhslichter will edit this comment with the correct information as it is finalized.
Mezzanine geometry/stackup
Connectors
Power rails
Power/IO header routing