RVV instruction `vsetvli` returns 0 for `vl`

[vmingchen]

I am playing with the vector support on my Lichee Pi 4A. But I could not get a simple assembly program with vector instruction working. The program is as follows:

$ cat vtype.S
.globl main
.section .text
.option arch, +v
main:
        li t0, 6
        vsetvli a0, t0, e64     # set a0 to vl which is the 1st arg to `_exit`
        li a7, 93               # set and invoke syscall '_exit'
        ecall
$ riscv64-linux-gnu-gcc -g vtype.S -o vtype -march=rv64imafdv && ./vtype
$ echo $?
0

I meant it to call the _exit syscall with the vl value as return value. But the return value is always zero.

According to the riscv-v-spec-0.7.1 doc,

If the vtype setting is not supported by the implementation, then the vill bit is set in vtype, the remaining bits in vtype are set to zero, and the vl register is also set to zero.

So, it suggests this simple vtype setting of e64 is not supported. How can we fix this and get RVV instructions working?

I am using the vanilla OS coming with the board:

$ uname -a
Linux lpi4a 5.10.113+ #1 SMP PREEMPT Wed Dec 20 08:25:29 UTC 2023 riscv64 GNU/Linux
$ cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1

processor       : 1
hart            : 1
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1

processor       : 2
hart            : 2
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1

processor       : 3
hart            : 3
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1

Thanks a lot!

[vmingchen]

It turned out that the RVV 0.7.1 version is not supported by the mainline gcc.

Use the gcc version here fix the problem: https://github.com/brucehoult/riscv-gnu-toolchain

$ cat vtype.S 
.globl main
.section .text
main:
        li t0, 6
        vsetvli a0, t0, e64     # set a0 to vl which is the 1st arg to `_exit`
        li a7, 93               # set and invoke syscall '_exit'
        ecall
$ /opt/rvv071/bin/riscv64-unknown-elf-gcc -g vtype.S -o vtype -march=rv64gcv && ./vtype
$ echo $?
2