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sipeed / bl602-hal

Hardware Abstract Layer for BL602 RISC-V WiFi + BLE SoC in embedded Rust
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SPI master implementation #18

Closed bjoernQ closed 3 years ago

bjoernQ commented 3 years ago

This adds SPI master functionality. (Only 8 bit transfers for now)

I tested this with a logic analyzer, loop back and an STM32F103 as SPI slave. It actually works so far but the SCLK frequency is half of what I configure - maybe someone sees where that problem is.

See https://github.com/bjoernQ/bl602-hal/blob/df148c17aed4ad76b7f42f6277a36d3cf3e640e7/src/spi.rs#L140

I was also not able to test with advanced clock settings since my currently only DT-BL10 seems to be somewhat faulty and acts weird in some regards. (More dev boards are ordered but they did not arrive yet)

9names commented 3 years ago

The SCLK frequency is half what you expect because the phase length values are double what they should be. If you check reference manual 1.2 page 116, they outline the length of phase 0 and 1 (low and high values for clock). Example: at 16MHz SPI clock, targeting an 8MHz freq, you set them to 1. So we spend 2 cycles high, 2 cycles low, and get a 4Mhz frequency. Refer to Reference Manual 1.4 page 116 for a diagram describing what I'm talking about

9names commented 3 years ago

In my testing following the example in your code, it appears that MOSI and MISO are swapped, at least for pins D0 and D1. Can you double check this?

bjoernQ commented 3 years ago

SCLK should now be as specified and MISO / MOSI pins should be as configured

9names commented 3 years ago

LGTM

luojia65 commented 3 years ago

LGTM