Open feldim2425 opened 5 years ago
btw: Connections:
Sipeed Risc-V debugger -> Maix M1w Dock
-------------------------------------------------------------
Pin 1 (TCK) -> Pin 0 (TCK) [Next to the USB Plug]
Pin 2 (GND) -> GND [Top Connector, Above the RST Pin]
Pin 3 (TDO) -> Pin 3 (TDO) [Next to the USB Plug]
Pin 5 (TMS) -> Pin 2 (TMS) [Next to the USB Plug]
Pin 7 (RST) -> RST [Top Connector]
Pin 9 (TDI) -> Pin 1 (TDI) [Next to the USB Plug]
Pins 4 (NC), 6 (TXD), 8 (RXD), 10 (GND) on the debugger are left unconnected
No connections to VCC on the Board. Powered by the USB-C Plug.
For anyone else seeing this issue, this is definitely a JTAG cable problem. Re-check all pins for continuity and short circuits.
Hello, strange that I do not see mention about disabling onboard STM32 for external debug on MAIX-GO. It is obvious that active STM32 interface will prevent successful debug via external probe. And I do observe this collision when trying to connect J-link. J-link could not pull JTAG lines to ground. So, there must be a way to disable STM32. Maybe by pulling reset down, but it is inconvenuet.
I disabled STM32 via BOOT0 during PowerON. Now I see correct oscillograms with J-link.
My output looks like:
Kendryte Open On-Chip Debugger For RISC-V v0.2.3 (2019-02-21) Licensed under GNU GPL v2 debug_level: 2 adapter speed: 1000 kHz Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. riscv.cpu Info : J-Link V9 compiled Sep 1 2016 18:29:50 Info : Hardware version: 9.20 Info : VTarget = 3.269 V Info : clock speed 1000 kHz Info : JTAG tap: riscv.cpu tap/device found: 0x04e4796b (mfg: 0x4b5 (<unknown>), part: 0x4e47, ver: 0x0) Core [0] halted at 0x404 due to software breakpoint Info : Examined RISCV core; found 2 harts Info : Listening on port 3333 for gdb connections Info : JTAG tap: riscv.cpu tap/device found: 0x04e4796b (mfg: 0x4b5 (<unknown>), part: 0x4e47, ver: 0x0) ** Programming Started ** **embedded:startup.tcl:476: Error: ** Programming Failed ** in procedure 'program' in procedure 'program_error' called at file "embedded:startup.tcl", line 532 at file "embedded:startup.tcl", line 476 *** [upload] Error 1**
Segger Jlink says that my J-link does not support this RISKV debug via JTAG. Could it be a reason?
PS
If I do not use upload via J-link, debug starts and works correctly. So Segger is no right.
What could be done?
To my surprise, if I do not declare upload_protocol everything works fine
I'm having the same problem with debugging using the Nexys A7 50T. Please have a look at the .doc file attached with this post and help me resolve this issue, nexys50t debug.docx
K210 TDO pin driving ability is too weak, not support some adapter without Isolated chip.
First test attached logic analyzer:
> .\openocd.exe -f .\jlink_kendryte.cfg
xPack OpenOCD x86_64 Open On-Chip Debugger 0.11.0+dev (2021-12-07-17:33)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'adapter speed' not 'adapter_khz'
Info : J-Link ARM V8 compiled Nov 28 2014 13:44:46
Info : Hardware version: 8.00
Info : VTarget = 3.300 V
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0xfe018389 (mfg: 0x1c4 (Satron Handelsges), part: 0xe018, ver: 0xf)
Warn : JTAG tap: riscv.cpu UNEXPECTED: 0xfe018389 (mfg: 0x1c4 (Satron Handelsges), part: 0xe018, ver: 0xf)
Error: JTAG tap: riscv.cpu expected 1 of 1: 0x04e4796b (mfg: 0x4b5 (Canaan-Creative Co Ltd), part: 0x4e47, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet
Second test:
> .\openocd.exe -f .\jlink_kendryte.cfg
xPack OpenOCD x86_64 Open On-Chip Debugger 0.11.0+dev (2021-12-07-17:33)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'adapter speed' not 'adapter_khz'
Info : J-Link ARM V8 compiled Nov 28 2014 13:44:46
Info : Hardware version: 8.00
Info : VTarget = 3.300 V
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x04e4796b (mfg: 0x4b5 (Canaan-Creative Co Ltd), part: 0x4e47, ver: 0x0)
Info : [riscv.cpu] Found 4 triggers
halted at 0x800b5256 due to debug interrupt
Info : Examined RISCV core; XLEN=64, misa=0x800000000014112d
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
K210 TDO pin driving ability is too weak, not support some adapter without Isolated chip.
First test attached logic analyzer:
> .\openocd.exe -f .\jlink_kendryte.cfg xPack OpenOCD x86_64 Open On-Chip Debugger 0.11.0+dev (2021-12-07-17:33) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html DEPRECATED! use 'adapter driver' not 'interface' DEPRECATED! use 'adapter speed' not 'adapter_khz' Info : J-Link ARM V8 compiled Nov 28 2014 13:44:46 Info : Hardware version: 8.00 Info : VTarget = 3.300 V Info : clock speed 1000 kHz Info : JTAG tap: riscv.cpu tap/device found: 0xfe018389 (mfg: 0x1c4 (Satron Handelsges), part: 0xe018, ver: 0xf) Warn : JTAG tap: riscv.cpu UNEXPECTED: 0xfe018389 (mfg: 0x1c4 (Satron Handelsges), part: 0xe018, ver: 0xf) Error: JTAG tap: riscv.cpu expected 1 of 1: 0x04e4796b (mfg: 0x4b5 (Canaan-Creative Co Ltd), part: 0x4e47, ver: 0x0) Error: Trying to use configured scan chain anyway... Warn : Bypassing JTAG setup events due to errors Error: dtmcontrol is 0. Check JTAG connectivity/board power. Warn : target riscv.cpu examination failed Info : starting gdb server for riscv.cpu on 3333 Info : Listening on port 3333 for gdb connections Error: Target not examined yet
Second test:
> .\openocd.exe -f .\jlink_kendryte.cfg xPack OpenOCD x86_64 Open On-Chip Debugger 0.11.0+dev (2021-12-07-17:33) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html DEPRECATED! use 'adapter driver' not 'interface' DEPRECATED! use 'adapter speed' not 'adapter_khz' Info : J-Link ARM V8 compiled Nov 28 2014 13:44:46 Info : Hardware version: 8.00 Info : VTarget = 3.300 V Info : clock speed 1000 kHz Info : JTAG tap: riscv.cpu tap/device found: 0x04e4796b (mfg: 0x4b5 (Canaan-Creative Co Ltd), part: 0x4e47, ver: 0x0) Info : [riscv.cpu] Found 4 triggers halted at 0x800b5256 due to debug interrupt Info : Examined RISCV core; XLEN=64, misa=0x800000000014112d Info : starting gdb server for riscv.cpu on 3333 Info : Listening on port 3333 for gdb connections Info : Listening on port 6666 for tcl connections Info : Listening on port 4444 for telnet connections
can you tell more details about how you made this?thanks
im using the rv debugger lite , and facing excatly the same problem
i have the same problem,using jlink ultra+ can not connect the k210 module。but can connect sipeed MAXbit (with chip)
I cannot use the sipeed-rv-debugger to debug my MaixDock. It outputs the following in the debug console:
I checked the connection multiple times they seem to be ok. platform.ini :
Operating System: Ubuntu 18.10