Open kamejoko80 opened 5 years ago
Hello kamejoko80!
Of course i will add missing modules. I couldn't test this module in real hardware so if you are able to test it please write me whenever you have any issues or questions.
Hello skatanik,
Thanks for your response.
Let me try to simulate your mipi controller first then test it on the real HW, but it takes time to prepare some things such as development kit, HW design.
Is there anyway to avoid vendor specific primitives usage in the design such as PLL, FIFO buffer... Is this source code just supports Altera FPGA only right ?
Yes, i was writing this controller for using with Altera FPGA. But actually the only Altera IP core i used is FIFO. This design uses single and dual clock FIFOs. But as you can see component altera_generic_fifo is just a wrapper for Altera FIFO IP cores, so if it is needed you can easily replace Altera FIFO in this wrapper with any other FIFO.
Hello skatanik,
Got it, I'll try and report the result when done. Thank you very much.
We had downloaded the project and intended to perform simulation with Quartus Modelsim. We first opened Quartus project "dsi_controller_test.qpf" then synthesis ("Start Analysis & Elaboration"). However, Quartus prompted "Tcl Script file top_level_system/synthesis/top_level_system.qip not find". So, would you mind providing the following information:
Occasionally i've moved this project to another repo: https://github.com/skatanik/hdmi2dsi_board unfortunately i didn't work with quartus project for a while because i switched to xilinx. But as i remember in quartus there is Nios II core inside, so first you need to compile binaries for it. And then just run testbench file.
Hi Skatanik,
Thank you for sharing the source code. I've tried to sysnthesize the source code by using Quartus Prime 18.0 but not successfull because of missing libraries
Would you please to provide them ?