Closed m1geo closed 2 years ago
Just the Arty top comment will do :)
// Interfaces: // BTN - Button 0, system reset. // SW[2] - PET diagnostic switch // SW[1] - PET turbo mode // SW[0] - PET suspend // LED - PET diagnostic LED. // VGA_R[3:0] - PMOD connections to JA and JB on Arty. The constraints // VGA_G[3:0] - file assigns these signals to the proper pins so as to // VGA_B[3:0] - interface to Digilent's PmodVGA PMOD board. // VGA_HSYNC - // VGA_VSYNC - // AUDIO - CB2 audio connected to JC[1]. // CASS_WR - Cassette write output connected to JC[3]. // CASS_RD - Cassette read input connected to JC[4]. // PS2_CLK - PS/2 clock connected to JD[3]. // PS2_DATA - PS/2 data connected to JD[1].
This was done on an original Arty which has an Artix-35T FPGA. It uses only about 6% (1194 / 20800) of the LUTs and 25% (12.5 / 50) of the block RAMs of a 35T so a 100T would overkill.
Thanks. I got it going! Just took a bit of digging through the Verilog and some tweaks to the XDC for my PMOD VGA 1.1. Thanks for the cool project! Useful learning material! :) 👍
Hey - really cool project. I have an Arty board here and was planning to give it a go! Could you add a bit more detail (just a table to show PMOD<>Cassette, PMOD<>PS/2, PMOD<>Sound. I see you have a simple diagram showing how the video is done.
Finally, what Arty version is needed? Will this work on the 35T or does it need 100T?
Cool project! Thanks :)