skibo
commented
3 days ago I'm sure it would be possible to run at 1Mhz but running at a higher clock (and pacing it with a 1Mhz pulse "slow_clock") allows for a "Turbo" mode that can be turned on on-the-fly. I also think it is good to design against a higher speed to learn what design choices work and don't work at normal FPGA clock rates.
The video output is VGA 640x480 @60hz so timing is slightly off compared to a real PET (thus the clock is off by 1%). There is source code in the project (pet2001vid.v) to produce PET compatible signals but I haven't tested it in a while and it looks like it needs the clock to be adjusted to 40Mhz so it can have a perfect 8Mhz pixel clock.
EDIT: 80Mhz-->40Mhz
Hi! I am looking at your code because part of it is used in the MiSTer PET core, and I am trying to collect enough knowledge to port it to the MEGA-65, using the Mister-2-Mega framework. This is all new to me to it requires to overcome some hurdles :)
While doing that, I noticed that your VIA, like many other implementations of 1 MHz chips, seems to run on a much faster clock than that, and "do stuff" on its edges. Sometimes combined with checking the 1 MHz clock, sometimes not. I suppose there is some reason for that, but I haven't found it. Naively I would think that if the original could run on just a 1 MHz clock, surely a reimplementation could too?
Also, in the video section (this part isn't used in the MiSTer PET core), the signal that signals the video retrace, and generates the 60 Hz vblank interrupt, seems to be starting and stopping slightly wrong. It is supposed to start just after the last displayable pixel on the bottom right, for exactly 3*20 lines (20 lines bottom border, 20 lines retrace, 20 lines top border), and therefore stop in the line before the first scanline with characters, also just to the right of the text area. See https://sourceforge.net/p/vice-emu/bugs/1954/ for more info. (The mister core has the same issue with its code, as far as I can see)