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skordal / potato

A simple RISC-V processor for use in FPGA designs.
BSD 3-Clause "New" or "Revised" License
256 stars 41 forks source link

[Synth 8-549] port width mismatch for port 'addra': port width = 11, actual width = 12 #10

Closed Sebas95 closed 6 years ago

Sebas95 commented 6 years ago

I'm trying to synthetize your SoC example, but I've got this error.

I've checked the block memory generator and says width is 11. I am using vivado 2017.4

Sebas95 commented 6 years ago

The issue was that I was using a depth of 2048 in port A (I was using an out-of-date manual) and actually needs 4096