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skordal / potato

A simple RISC-V processor for use in FPGA designs.
BSD 3-Clause "New" or "Revised" License
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How IRQ work in potato ? #3

Closed santhoshvlsi closed 8 years ago

santhoshvlsi commented 8 years ago

Hi , I have a doubts on IRQ :

What are the valid IRQ values to drive the core. How IRQ handing in potato core. Can u have any test case to check the IRQ.

Thank you,

Regards, Santhosh Kumar

skordal commented 8 years ago

Hi.

The IRQs are active-high signals provided to the processor core by the irq input. The core supports up to 8 IRQs. The interrupts are enabled individually by enabling the corresponding bit in bits 24-31 in the MIEregister, where bit 24 = IRQ0 and 31 = IRQ7. The IE bit in the MSTATUS works as a global interrupt enable bit and must be set for IRQs to function.

When processing an interrupt, bits 24-31 in the MIP register will indicate which of the IRQ lines are active so they can be handled, and in addition, the MCAUSE register will contain a value specifying which IRQ caused the processor to enter the interrupt handler.

An example of how to handle interrupts can be seen in benchmarks/sha256/main.c, in the exception_handler() function. It checks the MCAUSE register to see if the exception/interrupt was caused by IRQ5, which is connected to the timer.