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skordal / potato

A simple RISC-V processor for use in FPGA designs.
BSD 3-Clause "New" or "Revised" License
263 stars 41 forks source link

aee_rom is not found (not using Vivado) #9

Closed STAIRB closed 6 years ago

STAIRB commented 6 years ago

Hi Skordal,

I am trying to synthesize your SOC since I am trying to get into the riscv, however line 37 of aee_rom_wrapper.vhd you want to use aee_rom and u explain how to instantiate one using Vivado. Since I am not using Vivado I would like if you have made a version where you infer it?

Thank you.

skordal commented 6 years ago

Unfortunately, the example SoC is only supported in Vivado for now, since it requires the generated block RAM memory. The reason for using the block RAM generator to generate this memory is that the memory needs to be initialized with the application to be run, which is easier when using the generator.

STAIRB commented 6 years ago

Thank you for replying,

Do you think I can infer ram and then initialized to make at least the synthesis ? if yes where can I find the initialization values ?

skordal commented 6 years ago

That should probably work. The initialization values are generated when you run make in either software/hello or software/sha256, which will produce a .coe file which can be used.

STAIRB commented 6 years ago

Ok thank you.