Open skot opened 4 months ago
Clock streching Clock stretching is supported through a hack that re-uses the JTAG adaptative clock mode designed for ARM devices. FTDI HW drives SCL on AD0 (BD0), and samples the SCL line on : the 8th pin of a port AD7 (BD7).
When a FTDI device without an open collector capability is used (FT2232H, FT4232H, FT4232HA) the current sourced from AD0 may prevent proper sampling ofthe SCL line when the slave attempts to strech the clock. It is therefore recommended to add a low forward voltage drop diode to AD0 to prevent AD0 to source current to the SCL bus. See the wiring section.
Connected pins 16 and 24 and was able to get clock stretching to work and read the pic chip. you do have to play with delays but it seems like you have to no matter what. I did not have to change the clock speed with the right delays.
We need clock stretching mode to communicate with the PIC on S19j and earlier hashboards.. According to the pyftdi docs, the FT4232:
This should be U1 pins 16 & 24 pins connected. Ideally this can be hacked on a Bitcrane v2.3 manually to test if it indeed works.