The AMC LMK clock receives 122.88 MHz, cleans it up, then spits it
back out to the FPGA. To do this, it locks to one of two clocks,
CLKin0 or CLKin1. 0 is the FPGA's recovered timing clock, and 1 is the
front panel clock. Previously, with fiber timing, the LMK still tries
to lock to the front panel, fails, then free runs, preventing the
tones from locking to the fiber 122.88 MHz.
Solution
Set LMK 0x146 to 0x08 when taking timing from fiber. This also applies
to the backplane case, so set that as well.
Note this could be in the defaults .yml passed to Rogue, then just hit
Rogue with Init. But those defaults .yml files are hard to edit right
now, so edit them dynamically in pysmurf.
Tests
Tested using SLAC warm RF lab with v5.0.4, one LB in bay 0, fiber timing system.
Problem
The AMC LMK clock receives 122.88 MHz, cleans it up, then spits it back out to the FPGA. To do this, it locks to one of two clocks, CLKin0 or CLKin1. 0 is the FPGA's recovered timing clock, and 1 is the front panel clock. Previously, with fiber timing, the LMK still tries to lock to the front panel, fails, then free runs, preventing the tones from locking to the fiber 122.88 MHz.
Solution
Set LMK 0x146 to 0x08 when taking timing from fiber. This also applies to the backplane case, so set that as well.
Note this could be in the defaults .yml passed to Rogue, then just hit Rogue with Init. But those defaults .yml files are hard to edit right now, so edit them dynamically in pysmurf.
Tests
Tested using SLAC warm RF lab with v5.0.4, one LB in bay 0, fiber timing system.